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| MT90866 Flexible Digital Switch with H.110 Interface Data Sheet Features * * * * * * * * * * * * * * * * * 2,432 x 2,432 non-blocking switching among local streams 4,096 x 2,432 blocking switching between backplane and local streams 2,048 x 2,048 non-blocking switching among backplane streams Rate conversion between backplane and local streams Rate conversion among local streams Backplane interface accepts data rates of 8.192Mb/s or 16.384Mb/s Local interface accepts data rates of 2.048Mb/s, 4.096Mb/s or 8.192Mb/s Sub-rate switching (2 or 4 bits) configuration for local streams at a data rate of 2.048Mb/s Meets all the key H.110 mandatory signal requirements including timing Per-channel variable or constant throughput delay Per-stream input delay, programmable for local streams on a per bit basis Per-stream output advancement, programmable for backplane and local streams Per-channel direction control for backplane streams Per-channel message mode for backplane and local streams Per-channel high impedance output control for backplane and local streams Compatible to Stratum 4 Enhanced clock switching standard Integrated PLL conforms to Telcordia GR-1244-CORE Stratum 4 Enhanced switching standard -Holdover Mode with holdover frequency stability of 0.07ppm - Jitter attenuation from 1.52 Hz. - Time interval error (TIE) correction - Master and Slave mode operation Non-multiplexed microprocessor interface Connection memory block-programming for fast device initialization Tristate-control outputs for external drivers Pseudo-Random Binary Sequence (PRBS) pattern generation and testing for backplane and local streams Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard 3.3V operation with 5V tolerant inputs and I/O's 5V tolerant PCI driver on CT-Bus I/O's Ordering Information MT90866AG 344 Ball PBGA -40C to +85C December 2002 Applications * * * * * * * * Multi-service access platforms CTI applications/cPCI platform Carrier Class Gateways Integrated access services ST-BUS and H.110 interface applications Remote Access Servers Digital Loop Carriers Remote Access Concentrators Description The MT90866 Digital Switch provides switching capacities of 4,096 x 2,432 channels between backplane and local streams, 2,432 x 2,432 channels among local streams and 2,048 x 2,048 channels among backplane streams. The local connected serial inputs and outputs have 32, 64 and 128 64kb/s channels per frame with data rates of 2.048, 4.096 and 8.192Mb/s respectively. The backplane connected serial inputs and outputs have 128 and 256 64kb/s channels per frame with data rates of 8.192 and 16.384Mb/s respectively. The MT90866 also offers a sub-rate switching configuration which allows 2-bit wide 16kb/s or 4-bit wide 32kb/s data channels to be switched within the device. The device has features that are programmable on a per-stream or a per-channel basis including message mode, input delay offset, output advancement offset, direction control, and high impedance output control. The MT90866 supports all three of the H.110 specification required clocking modes: Primary Master, Secondary Master and Slave. * * * * * * * Zarlink Semiconductor Inc. 1 MT90866 VDD5V VDD VSS PCI_OE ODE Data Sheet STio0 Backplane Interface S/P & P/S Converter Backplane Data Memory (4,096 channels) Output Mux Local Interface P/S Converter HiZ Control STo0 STo27 LCSTo Local Connection Memory (2,432 locations) STio31 HiZ Control Output C20i TM1 TM2 SG1 AT1 DT1 BCSTo Local Data Memory (2,432 channels) Local Interface S/P Converter STi0 Mux APLL Backplane Connection Memory (4,096 locations) Local Interface Timing Unit STi27 ST_FPo0 ST_CKo0 ST_FPo1 ST_CKo1 RESET DPLL Internal Registers & Microprocessor Interface Test Port C8_A_io FRAME_A_io C8_B_io FRAME_B_io C32/64o C1M5o FAIL_PRI FAIL_SEC B_Active FAIL_A FAIL_B CTREF1 CTREF2 NREFo PRI_LOS SEC_LOS LREF7-0 A13-A0 DTA D15-D0 TMS TDi TDo TCK TRST DS CS R/W A_Active Figure 1 - Functional Block Diagram 2 Zarlink Semiconductor Inc. IC0-IC8 Data Sheet MT90866 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A STio VDD5V 14 STio 13 STio 12 STio 9 STio 6 STio 5 STio 4 VDD5V VDD5V STio 17 GND STio 19 STio 18 STio 16 GND STio 22 STio 21 STio 20 VDD STio 25 STio 24 STio 23 GND STio 26 STio 27 STio 28 VDD STio 31 STio 30 STio 29 GND VDD5V PCI_ OE GND STi2 STi3 STi8 STi9 STi12 STi13 STi16 STi21 STi22 STi24 STi26 A B STi1 STi5 STi6 STi10 GND STi14 STi17 STi20 STi23 STi25 STi27 B C STio 15 STio 10 STio 7 STio 2 STio 0 GND GND STio 11 STio 8 STio 3 STio 1 GND STi0 STi4 STi7 STi11 GND STi15 STi18 STi19 GND GND GND C D VDD GND VDD VDD GND VDD GND VDD GND GND STo0 STo1 D E VDD VDD LCSTo STo2 STo3 E F GND GND GND GND GND GND GND GND STo4 STo5 STo6 F G VDD GND GND GND GND GND GND GND GND VDD STo8 STo9 STo7 G H GND GND GND GND GND GND GND GND GND GND GND GND STo10 STo11 STo13 H J DTA BCSTo D15 VDD GND GND GND GND GND GND GND GND GND GND VDD STo12 STo14 STo15 J K D12 D13 D14 VDD GND GND GND GND GND GND GND GND GND GND GND STo16 STo17 STo21 STo18 K L D9 D10 D11 GND GND GND GND GND GND GND GND GND GND GND VDD STo20 STo19 L M D6 D7 D8 VDD GND GND GND GND GND GND GND GND GND GND VDD STo22 STo23 STo24 M N D5 D3 D4 GND GND GND GND GND GND GND GND GND GND GND GND STo27 STo26 STo25 N P D2 D1 D0 VDD GND GND GND GND GND GND GND GND VDD GND B_Act ive C8_A_io A_Act ive Frame_ A _io P R GND GND GND GND GND GND GND GND GND GND GND ODE R T A13 A12 A11 VDD VDD Frame_ C8_B_io Fail_A B _io Fail_B CTREF1 CTREF2 ST_ CKo0 GND ST_ FPo0 GND T U A10 A9 A8 GND VDD GND VDD GND VDD VDD GND VDD GND APLL VDD C64 BYPS C20i VDD APLL GND GND VDD GND U V CS A7 A5 A2 RESET TCK IC2 IC4 ST_ FPo1 ST_ CKo1 8 IC6 IC3 TM1 GND LREF5 LREF2 NREFo GND V W DS A6 A3 A0 TMS TDi IC5 IC7 SG1 AT1 GND FAIL_ LREF6 LREF3 LREF0 PRI C32o W Y R/W 1 A4 A1 TDo TRST 5 IC0 IC1 7 IC8 TM2 DT1 GND FAIL_ C1M5o Sec_Los Pri_Los SEC LREF7 LREF4 LREF1 14 15 16 17 18 19 20 Y 2 3 4 6 9 10 11 12 13 Top View 1 - A1 corner is identified by metallized markings. Figure 2 - 27mm x 27mm PBGA (JEDEC MO-151) Pinout Zarlink Semiconductor Inc. 3 MT90866 Ball Signal Assignment Ball Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Signal Name STIO14 VDD5V STIO17 STIO19 STIO22 STIO25 STIO26 STIO31 VDD5V STI2 STI3 STI8 STI9 STI12 STI13 STI16 STI21 STI22 STI24 STI26 STIO13 VDD5V GND STIO18 STIO21 STIO24 STIO27 STIO30 PCI_OE STI1 STI5 STI6 STI10 GND STI14 STI17 STI20 STI23 STI25 Ball Number B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Signal Name STI27 STIO12 STIO15 GND STIO16 STIO20 STIO23 STIO28 STIO29 GND STI0 STI4 STI7 STI11 GND STI15 STI18 STI19 GND GND GND STIO9 STIO10 STIO11 GND VDD GND VDD GND VDD GND VDD VDD GND VDD GND VDD GND GND STO0 Ball Number D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F8 F9 F10 F11 F12 F13 F17 F18 F19 F20 G1 G2 G3 G4 G7 G8 G9 G10 G11 G12 G13 G14 G17 G18 G19 G20 H1 Data Sheet Signal Name STO1 STIO6 STIO7 STIO8 VDD VDD LCSTO STO2 STO3 STIO5 STIO2 STIO3 GND GND GND GND GND GND GND GND STO4 STO5 STO6 STIO4 STIO0 STIO1 VDD GND GND GND GND GND GND GND GND VDD STO8 STO9 STO7 VDD5V 4 Zarlink Semiconductor Inc. Data Sheet Ball Number H2 H3 H4 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H17 H18 H19 H20 J1 J2 J3 J4 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J17 J18 J19 J20 K1 K2 K3 K4 K6 Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND STO10 STO11 STO13 DTA BCSTO D15 VDD GND GND GND GND GND GND GND GND GND GND VDD STO12 STO14 STO15 D12 D13 D14 VDD GND Ball Number K7 K8 K9 K10 K11 K12 K13 K14 K15 K17 K18 K19 K20 L1 L2 L3 L4 L6 L7 L8 L9 L10 L11 L12 L14 L15 L17 L18 L19 L20 M1 M2 M3 M4 M6 M7 M8 M9 M10 M11 Signal Name GND GND GND GND GND GND GND GND GND GND STO16 STO17 STO18 D9 D10 D11 GND GND GND GND GND GND GND GND GND GND VDD STO20 STO21 STO19 D6 D7 D8 VDD GND GND GND GND GND GND Ball Number M12 M13 M14 M15 M17 M18 M19 M20 N1 N2 N3 N4 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N18 N19 N20 P1 P2 P3 P4 P7 P8 P9 P10 P11 P12 P13 P14 P17 P18 P19 MT90866 Signal Name GND GND GND GND VDD STO22 STO23 STO24 D5 D3 D4 GND GND GND GND GND GND GND GND GND GND GND STO27 STO26 STO25 D2 D1 D0 VDD GND GND GND GND GND GND GND GND VDD GND B_ACTIVE Zarlink Semiconductor Inc. 5 MT90866 Ball Number P20 R1 R2 R3 R4 R8 R9 R10 R11 R12 R13 R17 R18 R19 R20 T1 T2 T3 T4 T17 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 Signal Name A_ACTIVE GND GND GND GND GND GND GND GND GND GND GND ODE C8_A_IO FRAME_A_IO A13 A12 A11 VDD VDD C8_B_IO FAIL_A A10 A9 A8 GND VDD GND VDD GND VDD VDD GND VDD GND VDD GND VDD GND FAIL_B Ball Number U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 Signal Name CTREF1 CTREF2 CS A7 A5 A2 RESET TCK IC2 IC4 IC6 IC3 TM1 GND APLLVDD APLLGND LREF5 LREF2 NREFO GND ST_CKo0 ST_FPo0 DS A6 A3 A0 TMS TDi IC5 ST_FPo1 IC7 SG1 AT1 GND C64BYPS FAIL_PRI LREF6 LREF3 LREF0 C32O Ball Number W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Data Sheet Signal Name GND GND R/W A4 A1 TDo TRST IC0 IC1 ST_CKo1 IC8 TM2 DT1 GND C20I FAIL_SEC LREF7 LREF4 LREF1 C1M5O SEC_LOS PRI_LOS 6 Zarlink Semiconductor Inc. Data Sheet Pin Description PBGA Ball Number D5, D7, D9, D11, D12, D14, D16, E4, E17, G4, G17, J4, J17, K4, L17, M4, M17, P4, P17, T4, T17,U5, U7, U9, U10, U12, U14, U16 A2,A9,B2,H1 Name VDD +3.3 Volt Power Supply. Description MT90866 VDD5V +5.0V/+3.3V Power Supply. If 5V power supply is tied to these pins, STio0-31 pins will meet 5V PCI requirements. If 3.3V power supply is tied to these pins, STio0-31 pins will meet 3.3V PCI requirements. Ground. B3, B14,C3, C9, C14, C18, C19, C20, D4, D6, D8, D10, D13, D15, D17, D18, F4, F8-F13, F17, G7-G14, H2, H3, H4, H6-H15, H17, J6-J15, K6-K15, K17, L4, L6-L15, M6-M15, N4, N6-15, N17, P7-P14, P18, R1, R2, R3, R4, R8-R13, R17, U4, U6, U8, U11, U13, U15, U17, V12, V18, W12, W19, W20, Y12 V13 V14 V5 VSS APLLVDD APLLVss RESET +3.3 Volt Analog PLL Power Supply. No special filtering is required for this pin. Analog PLL Ground Device Reset (5V Tolerant Input). This input (active low) puts the device in its reset state; this state clears the device's internal counters and registers. To ensure proper reset action, the reset pin must be low for longer than 400 ns. To ensure proper operation, a delay of 100s must be applied before the first microprocessor access is performed after the RESET pin is set high. The device reset also tristates STo0-27 and STio0-31, and sets the LCSTo and BCSTo pins. When in a RESET condition, the C8_A_io, FRAME_A_io, C8_B_io, and FRAME_B_io signals are tri-stated. Serial Input/Output Streams 0 - 15 (5V Tolerant PCI I/Os). In H.110 mode, these pins accept serial TDM data streams at 8.192Mb/s with 128 channels per stream. In the 16Mb/s mode, these pins accept serial TDM data streams at 16.384Mb/s with 256 channels per stream respectively. G2, G3, F2, F3, G1, F1, E1, E2, E3, D1, D2, D3, C1, B1, A1, C2 STio0-3, STio4-7, STio8-11, STio12-15 Zarlink Semiconductor Inc. 7 MT90866 Pin Description (continued) PBGA Ball Number C4, A3, B4, A4, C5, B5, A5, C6, B6, A6, A7, B7, C7, C8, B8, A8 C10, B10, A10, A11 Name STio16 - 19, STio20 - 23, STio24 - 27, STio28 - 31 STi0-3 Description Data Sheet Serial Input/Output Streams 16 - 31 (5V Tolerant PCI I/Os). In H.110 mode, these pins accept serial TDM data streams at 8.192Mb/s with 128 channels per stream. In the 16Mb/s mode, these pins are tristated internally and should be connected to ground. Serial Input Streams 0 - 3 (5V Tolerant Inputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these inputs accept data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these inputs accept a data rate of 2.048Mb/s. Serial Input Streams 4 - 7 (5V Tolerant Inputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these inputs accept data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these inputs accept a data rate of 2.048Mb/s. Serial Input Streams 8 - 11 (5V Tolerant Inputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these inputs accepts data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these inputs accept a data rate of 2.048Mb/s. Serial Input Streams 12 - 15 (5V Tolerant Inputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these inputs accept data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these inputs accept a data rate of 2.048Mb/s. Serial Input Streams 16 - 27 (5V Tolerant Inputs). In 2Mb/s mode, these inputs accept data rates of 2.048Mb/s with 32 channels per stream respectively. In 4Mb/s or 8Mb/s mode, the STi16 - 18 inputs accept data rates of 4.096 or 8.192Mb/s with 64 or 128 channels per stream respectively. In 4Mb/s or 8Mb/s mode the STi19 - 27 inputs should be low. No sub-rate switching mode is offered for STi16-27. Serial Output Streams 0 - 3 (5V Tolerant Tri-State Outputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these outputs have data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these outputs have a data rate of 2.048Mb/s. Serial Output Streams 4 - 7 (5V Tolerant Tri-State Outputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these outputs have data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these outputs have a data rate of 2.048Mb/s. Serial Output Streams 8 - 11 (5V Tolerant Tri-State Outputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these outputs have data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these outputs have a data rate of 2.048Mb/s. Serial Output Streams 12 - 15 (5V Tolerant Tri-State Outputs). In 2Mb/s, 4Mb/s or 8Mb/s mode, these outputs have data rates of 2.048, 4.096 or 8.192Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit sub-rate modes, these outputs have a data rate of 2.048Mb/s. C11, B11, B12, C12 STi4 - 7 A12, A13, B13, C13 STi8 - 11 A14, A15, B15, C15 STi12 - 15 A16, B16, C16, C17, B17, A17, A18, B18, A19, B19, A20, B20 STi16 - 27 D19, D20, E19, E20 STo0 - 3 F18, F19, F20, G20 STo4 - 7 G18, G19, H18, H19 STo8 - 11 J18, H20, J19, J20 STo12 - 15 8 Zarlink Semiconductor Inc. Data Sheet Pin Description (continued) PBGA Ball Number K18, K19, K20, L20, L18, L19, M18, M19, M20, N20, N19, N18 Name STo16 - 27 Description MT90866 Serial Output Streams 16 to 27 (5V Tolerant Tri-state Outputs). In 2Mb/s mode, these outputs have data rate of 2.048 Mb/s with 32 channels per stream. In 4Mb/s or 8Mb/s mode, the STo16 - 18 outputs have data rates of 4.096Mb/s or 8.192Mb/s with 64 or 128 channels per stream respectively; STo19 - 27 are tri-stated. No sub-rate switching mode is offered for STo16-27. Output Drive Enable (5V Tolerant Input). When this pin is low, STo0 to STo27, STio0 to STio31, C1M5o, C32/64o, ST_CKo0, ST_CKo1, ST_FPo0 and ST_FPo1 outputs are all in high-impedance state. When ODE is high all of the aforementioned pins are active. Backplane Control Signal (Output). This pin is used for backplane external tristate controllers. When this signal is high, the corresponding output channels are in a high impedance state. BCSTo's bit rate is 32.768MHz. Local Control Signal (Output). This pin is used for local external tristate control. When this signal is high, the corresponding ouput channels are in a high impedance state. The bit rate is 32.768MHz. Master Clock (5V Tolerant Input). This pin accepts a 20.000 MHz clock. Clock A (5V Tolerant I/O). This is a 8.192MHz clock with 50% duty cycle. R18 ODE J2 BCSTo E18 LCSTo Y13 R19 R20 P20 C20i C8_A_io FRAME_A_io Frame Reference A (5V Tolerant I/O). This is a 122 ns wide, negative pulse, with 125us period. A_Active A Clock Active Indicator (5V Tolerant Output): This pin indicates whether the C8_A_io and the FRAME_A_io pins are inputs or outputs. When Bit 13 of the DOM1 register is low, this pin drives low and the C8_A_io and FRAME_A_io output drivers are disabled. When Bit 13 of the DOM1 register is high, this pin drives high and the C8_A_io and FRAME_A_io output drivers are enabled. Clock B (5V Tolerant I/O). This is a 8.192MHz clock with 50% duty cycle. T19 T18 P19 C8_B_io FRAME_B_io Frame Reference B (5V Tolerant I/O). This is a 122 ns wide, negative pulse, with 125us period. B_Active B Clock Active Indicator (5V Tolerant Output): This pin indicates whether the C8_B_io and the FRAME_B_io pins are inputs or outputs. When Bit 14 of the DOM1 register is low, this pin drives low and the C8_B_io and FRAME_B_io output drivers are disabled. When Bit 14 of the DOM1 register is high, this pins drives high and the C8_B_io and FRAME_B_io output drivers are enabled. A Failure (Output). When the C8_A_io or the FRAME_A_io signal fails, this signal goes to high. B Failure (Output). When the C8_B_io or the FRAME_B_io signal fails, this signal goes to high. CT-Bus Reference 1 (5V Tolerant Input). This pin accepts 8KHz, 1.544MHz or 2.048MHz network timing reference. CT-Bus Reference 2 (5V Tolerant Input). This pin accepts 8KHz, 1.544MHz or 2.048MHz network timing reference. Zarlink Semiconductor Inc. 9 T20 U18 U19 U20 FAIL_A FAIL_B CTREF1 CTREF2 MT90866 Pin Description (continued) PBGA Ball Number W17, Y17, V16, W16, Y16, V15, W15, Y15 V17 Name LREF0- 7 Description Data Sheet Local Reference (5V Tolerant Inputs). These pins accept 8KHz, 1.544MHz or 2.048MHz local timing reference. Network Reference Output (Output). Any local reference can be switched to this output. The output data rate can be either the same as the selected reference input data rate or divided to be 8KHz. Primary Reference Lost (5V Tolerant Input). When this signal is high, it indicates that PRIMARY REFERENCE is not valid. Combined with SEC_LOS input, this input pin is used in the External Reference Switching Mode of the DPLL. Secondary Reference Lost (5V Tolerant Input). When this signal is high, it indicates that SECONDARY REFERENCE is not valid. Combined with the PRI_LOS input, this input pin is used in the External Reference Switching Mode of the DPLL. Primary Reference Failure (5V Tolerant Output). This pin reflects the logic status of the PLS bit of the DPLL House Keeping Register (DHKR). When the primary reference fails, this signal goes to 1. Secondary Reference Failure (5V Tolerant Output). This pin reflects the logic status of the SLS bit of the DPLL House Keeping Register (DHKR). When the secondary reference fails, this signal goes to 1. C32/64o Clock (5V Tolerant Output). A 32.768MHz output clock when the DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the DPLL Clock Monitor register bit (CKM) is high. C1.5o Clock (5V Tolerant Output). A 1.544MHz output clock. ST-Bus Frame Pulse Output (5V Tolerant Output). The width of this output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is 8KHz. ST-Bus Clock Output (5V Tolerant Output). The frequency of this output ST-Bus clock can be 4.096MHz, 8.192MHz or 16.384MHz. ST-Bus Frame Pulse Output (5V Tolerant Output). The width of this output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is 8KHz. ST-Bus Clock Output (5V Tolerant Output). The frequency of this output ST-Bus clock can be 4.096MHz, 8.192MHz or 16.384MHz. Chip Select (5V Tolerant Input). This active low input is used by the microprocessor to access the microport. Data Strobe (5V Tolerant Input). This active low input works in conjunction with CS to initiate the read and write cycles. Read/Write (5V Tolerant Input). This input controls the direction of the data bus lines (D0 - D15) during the microprocessor access. NREFo Y20 PRI_LOS Y19 SEC_LOS W14 FAIL_PRI Y14 FAIL_SEC W18 C32/64o Y18 V20 C1M5o ST_FPo0 V19 W8 ST_CKo0 ST_FPo1 Y8 V1 W1 Y1 ST_CKo1 CS DS R/W 10 Zarlink Semiconductor Inc. Data Sheet Pin Description (continued) PBGA Ball Number W4, Y3, V4, W3, Y2, V3, W2, V2, U3, U2, U1, T3, T2, T1 P3, P2, P1, N2, N3, N1, M1, M2, M3, L1, L2, L3, K1, K2, K3, J3 J1 Name A0 - A13 Description MT90866 Address 0 - 13 (5V Tolerant Inputs). These are the address lines to the internal memories and registers. D0 - D15 Data Bus 0 - 15 (5V Tolerant I/Os). These pins form the 16-bit data bus of the microport. DTA Data Transfer Acknowledge (5V Tolerant Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor is required to hold a high level. PCI Output Enable (3.3V Tolerant Input). This active low input is the control signal used to tristate the STio0 - 31 pins during hot-swapping. During normal operation this signal should be low. PLL Bypass Clock Input (5V Tolerant Input). Used for device testing. In functional mode, this input MUST be low. APLL Test Pin 1 (3.3V Input). Use for APLL testing only. In normal operation, this input should be connected to ground. APLL Test Pin 2 (3.3V Input). Use for APLL testing only. In normal operation, this input should be connected to ground. APLL Test Control (3.3V Input). Use for APLL testing only. In normal operation, this input should be connected to ground. Analog Test Access (5V Tolerant I/O). Use for APLL testing only. No connection for normal operation. Digital Test Access Output (5V Tolerant Output). Use for APLL testing only. No connection for normal operation. Test Mode Select (3.3V Input with Internal pull-up). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. Test Serial Data In (3.3V Input with Internal pull-up). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. Test Serial Data Out (3.3V Tolerant Tri-state Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Test Clock (5V Tolerant Input). Provides the clock to the JTAG test logic. This pin should be low when JTAG is not enabled. Test Reset (3.3V Input with Internal pull-up). Asynchronously initializes the JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin should be pulled low to ensure that the MT90866 is in normal functional mode. Leave unconnected for normal operation. Leave unconnected for normal operation. 11 B9 PCI_OE W13 V11 Y10 W10 W11 Y11 W5 C64BYPS TM1 TM2 SG1 AT1 DT1 TMS W6 TDi Y4 TDo V6 Y5 TCK TRST Y6 Y7 IC0 IC1 Zarlink Semiconductor Inc. MT90866 Pin Description (continued) PBGA Ball Number V7 V10 V8 W7 V9 W9 Y9 Name IC2 IC3 IC4 IC5 IC6 IC7 IC8 Description In normal operation this pin MUST be connected to ground. Leave unconnected for normal operation. Leave unconnected for normal operation. Leave unconnected for normal operation. Leave unconnected for normal operation. Leave unconnected for normal operation. Leave unconnected for normal operation. Data Sheet 12 Zarlink Semiconductor Inc. Data Sheet 1.0 Application Overview MT90866 The MT90866 is intended for carrier-grade applications that require medium bandwidth switching capability. The MT90866 meets the H.110 key signal and timing requirements, suitable for a compact PCI platform. While the Computer Telephony Interface (CTI) industry is adopting the compact PCI platform over VME, many manufacturers of telecom and datacom equipment are also selecting this platform. The compact PCI platform offers attractive features such as hot swappable cards, integrated PCI and H.110 TDM buses, and a rugged backplane and mechanical design. This new standard is replacing the older ribbon-cable based bus standards such as MVIP-90, H-MVIP and SCbus. Carrier-grade access, switching platforms, wireless base stations, and gateways (i.e. VOIP) may handle multiple T1/E1, DS-3 or OC-3 streams for connection to the WAN or PSTN. Multiple lower bandwidth interfaces are consolidated into these higher bandwidth pipes for networking into a WAN or PSTN. See Figure 3, "Typical Network Block Diagram" on page 13. Customer Premise Equipment PBX Access Network Core/Transport Analog Phones Branch Gateway 10 Base T Multiservice Access Concentrators Carrier Class Switch IP 10 Base T Ethernet Phone Enterprises IAD Edge Router Terabit Routers ATM ATM Edge Switch Residences Cable SOHO Gateway Base Stations Head End ATM Core Switches Base Station Controller Figure 3 - Typical Network Block Diagram Zarlink Semiconductor Inc. 13 MT90866 Data Sheet While these types of equipment serve different applications and markets, many share a similar type of internal architecture. Frequently a mid-plane or backplane configuration is used, which may accommodate a TDM bus, for compatibility to TDM interfaces (ISDN, Sonet, T1/E1, etc.), and a PCI bus, for interfacing to LAN networks and the IP network. In many cases, a Utopia bus may be present if ATM is used as an uplink to the WAN or PSTN. Interfacing into this midplane or backplane would be lower bandwidth subscriber line cards and higher bandwidth WAN uplink line cards. See Figure 4, "Carrier Multi-service Access Switch" on page 14. By locating TDM switching on the line card itself, as opposed to a centralized switching card, system designers employ a distributed switching arrangement. In this case, the MT90866 allows for local to backplane switching of DS-0 traffic from trunks or local connection such as internal DSP cards (compression, echo cancellation, modem termination). Unique to the industry, the MT90866 provides backplane switching, eliminating the need to move the traffic to the local streams and back. This feature allows users to move traffic among the backplane traces for routing to other destinations. On the uplink line card side, the MT90866 allows the users to interface to multiple T1 or E1 or DS-3 or OC-3 ports. With the ability to take 2,432 channels from 4,096 channels on the backplane and to switch them to the local streams, the MT90866 satisfies these higher bandwidth applications. Depending on the application, the CPE or access equipment may need to terminate internet traffic and switch the traffic to the appropriate destination. Most of these applications employ banks of DSP's to handle the modem calls. When the local streams are used to route traffic to these DSP cards, the application requires a high local switching capability on each card. This requirement is easily handled by the MT90866 with its local switching capacity of 2,432 channels. Zarlink Component Local Loop Access: To subscribers/customers T1/E1 Carrier Data Network Aggregation: To network/WAN T1/E1 UTOPIA Backplane Packet Backplane TDM Backplane T3/E3 T3/E3 SONET SONET ATM ATM ISDN VDSL PLL's VEC's SWITCHING CPU DSP'S RAM Figure 4 - Carrier Multi-service Access Switch 14 Zarlink Semiconductor Inc. Data Sheet 2.0 Device Overview MT90866 The MT90866 can switch up to 4,096 x 2,432 channels while providing a rate conversion capability. It is designed to switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local switching applications. The device maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel basis. The backplane interface can operate at 8.192Mb/s in CT-Bus mode or 16.384Mb/s in ST-BUS mode and is arranged in 125s wide frames that contain 128 or 256 channels respectively. A built-in rate conversion circuit allows users to interface between backplane and local interfaces which operates at 2.048Mb/s, 4.096Mb/s or 8.192Mb/s. When the device is in the local sub-rate switching mode, 2-bit 16kb/s or 4-bit 32kb/s data channels can be switched within the device. The local sub-rate switching mode is available in 2Mb/s mode only. By using Zarlink's message mode capability, the microprocessor can access input and output time slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. 2.1 Functional Description A Functional Block Diagram of the MT90866 is shown in Figure 1, "Functional Block Diagram" on page 2. It is designed to interface CT-Bus and ST-BUS serial streams from a backplane source and ST-BUS serial streams from a local source. 2.1.1 Frame Alignment Timing In the ST-BUS or the CT-Bus mode, the C8_A_io or C8_B_io pin accepts an 8.192MHz clock for the frame pulse alignment. The FRAME_A_io or FRAME_B_io is the frame pulse signal which goes low at the frame boundary for 122ns. The frame boundary is defined by the rising edge of the C8_A_io or C8_B_io clock during the low cycle of the frame pulse. Figure 5, "CT-Bus Timing for 8Mb/s Backplane Data Streams" on page 15 is the CT-Bus timing for the backplane 8.192Mb/s data streams and Figure 6, "ST-Bus Timing for 16Mb/s Backplane Data Streams" on page 16 is the ST-BUS timing for the 16.384Mb/s backplane data stream. FRAME_A_io, FRAME_B_io (CT Frame) C8_A_io, C8_B_io (8.192MHz) Channel 0 Channel 127 2 1 0 6 5 4 3 2 1 0 7 STio 0 - 31 (8Mb/s mode) 1 0 7 6 5 4 3 Figure 5 - CT-Bus Timing for 8Mb/s Backplane Data Streams Zarlink Semiconductor Inc. 15 MT90866 FRAME_A_io, FRAME_B_io (CT Frame) C8_A_io, C8_B_io 8.192MHz Ch 255 Channel 0 Channel 1 Channel 254 Data Sheet Channel 255 Ch 0 STio 0 - 15 (16Mb/s mode) 32107654321076543210 654321076543210765 Figure 6 - ST-Bus Timing for 16Mb/s Backplane Data Streams 2.1.2 Switching Configuration The device has two operation modes at different data rates for the backplane interface and five operation modes for the local interface. These modes can be programmed via the Device Mode Selection (DMS) register. Mode selections between the backplane and local interfaces are independent. 2.1.3 Backplane Interface The backplane interface can be programmed to accept data streams of 8Mb/s or 16Mb/s. When H.110 mode is enabled, STio0 to STio31 have a data rate of 8.192Mb/s. When ST-BUS mode is enabled, STio0 to STio15 have a data rate of 16.384Mb/s. Table 1 on page 16 describes the data rates and mode selections for the backplane interface. 2.1.4 Local Interface Five operation modes, 2Mb/s, 4Mb/s, 8Mb/s, 2-bit sub-rate and 4-bit sub-rate switching, can be selected for the local ST-BUS interface. The local interface is divided into five groups. Group 0 contains STi/STo0-3, Group 1 contains STi/STo4-7, Group 2 contains STi/STo8-11, Group 3 contains STi/STo12-15 and Group 4 contains STi/STo16-27. Each group can be selected individually through the Device Mode Selection (DMS) register. Streams belonging to the same group have the same operation mode. For Groups 0 to 3, any one of the five operation modes can be selected. Input data streams STi0-15 and output data streams, STo0 -15 can be selected according to the group to which they belong. STi16-27 and output data streams STo16-27 belong to Group 4 and can operate in 2Mb/s mode. In Group 4, only input data streams Sti16-18 and output data streams Sto16-18 can operate in 4Mb/s and 8Mb/s mode. No sub-rate modes are available for Group 4 data streams. See Table 2 on page 17 to Table 6 on page 18 for a description of the data rates and mode selection for the local ST-BUS interface. BMS bit of the DMS Register 0 1 Modes 8.192Mb/s 16.384Mb/s Table 1 - Mode Selection for Backplane Streams Backplane Interface STio0 - 31 STio0 - 15 16 Zarlink Semiconductor Inc. Data Sheet DMS Register Bits LG02 0 0 0 0 1 LG01 0 0 1 1 0 LG00 0 1 0 1 0 MT90866 Modes 8.192Mb/s 4.096Mb/s 2.048Mb/s 4-bit subrate 2-bit subrate STi0 - 3, STo0 - 3 Usable Streams Table 2 - Mode Selection for Local STi0 - 3 and STo0 - 3 Streams, Group 0 DMS Register Bits LG12 0 0 0 0 1 LG11 0 0 1 1 0 LG10 0 1 0 1 0 Modes 8.192Mb/s 4.096Mb/s 2.048Mb/s 4-bit subrate 2-bit subrate Usable Streams STi4 - 7, STo4 -7 Table 3 - Mode Selection for Local STi4 - 7 and STo4 - 7 Streams, Group 1 DMS Register Bits LG22 0 0 0 0 1 LG21 0 0 1 1 0 LG20 0 1 0 1 0 Modes 8.192Mb/s 4.096Mb/s 2.048Mb/s 4-bit subrate 2-bit subrate Usable Streams STi8 - 11, STo8 - 11 Table 4 - Mode Selection for Local STi8 - 11 and STo8 - 11 Streams, Group 2 DMS Register Bits LG32 0 0 0 0 1 LG31 0 0 1 1 0 LG30 0 1 0 1 0 Modes 8.192Mb/s 4.096Mb/s 2.048Mb/s 4-bit subrate 2-bit subrate STi12-15, STo12-15 Usable Streams Table 5 - Mode Selection for Local STi12 - 15 and ST012 - 15 Streams, Group 3 Zarlink Semiconductor Inc. 17 MT90866 DMS Register Bits LG41 0 0 1 LG40 0 1 0 Modes 8.192Mb/s 4.096Mb/s 2.048Mb/s Data Sheet Usable Streams STi16 - 18, STo16 - 18 STi16 - 27, STo16 - 27 Table 6 - Mode Selection for Local STi16 - 27 and STo16 - 27 Streams, Group 4 2.1.5 Local Input Delay Selection The local input delay selection allows individual local input streams to be aligned and shifted against the input frame pulse (FRAME_A_io or FRAME_B_io). This feature compensates for the variable path delays in the local interface. Such delays can occur in large centralized and distributed switching system. Each local input stream can have its own bit delay offset value by programming the local input bit delay selection registers (LIDR0 to LIDR9). See Table 12, "Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits" on page 48, for the contents of these registers. Possible bit adjustment can range up to +7 3/4 bit periods forward with resolution of 1/4 bit period. See Table 13 on page 48 and Figure 21 on page 49 for local input delay programming. 2.1.6 Output Advancement Selection The MT90866 allows users to advance individual backplane or local output streams with respect to the frame boundary. This feature is useful in compensating variable output delays caused by various output loading conditions. Each output stream can have its own advancement value programmed by the output advancement registers. The backplane output advancement registers (BOAR0 to BOAR3) are used to program the backplane output advancement. The local output advancement registers (LOAR0 to LOAR3) are used to program the local output advancement. Possible adjustment for local and backplane output data streams is 22.5 ns with a resolution of 7.5 ns. The advancement is independent of the output data rate. Table 14 on page 50 and Figure 22, "Example of Backplane Output Advancement Timing" on page 50, and Table 15 on page 51 and Figure 23, "Local Output Advancement Timing" on page 51 describe the details of the output advancement programming for the backplane and local interfaces respectively. 2.1.7 Memory Block Programming The MT90866 block programming mode (BPM) register provides users with the capability of initializing the local and backplane connection memories in two frames. The local connection memory is partitioned into high and low parts. Bit 13 - bit 15 of every backplane connection memory location will be programmed with the pattern stored in bit 6 bit 8 of the BPM register. Bit 13 - bit 15 of every local connection memory low location will be programmed with the pattern stored in bits 3 to 5 of the BPM register. The other bit positions of the backplane connection memory, the local low connection memory and all bits of the local high connection memory are loaded with zeros. See Figure 7, "Block Programming Data in the Connection Memories" on page 19 for the connection memory contents when the device is in block programming mode. The block programming mode is enabled by setting the memory block program (MBP) bit of the Control register to high. After the block programming enable (BPE) bit of the BPM register is set to high, the block programming data will be loaded into bits 13 to 15 of every backplane connection memory location and bits 13 to 15 of every local connection memory low location. The other connection memory bits are loaded with zeros. When the memory block programming is completed, the device resets the BPE bit to low. See Table 11 on page 46 for the bit assignment of the BPM register. 2.2 Delay Through the MT90866 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time slot interchange functions with different throughput delay 18 Zarlink Semiconductor Inc. Data Sheet MT90866 capabilities on a per-channel basis. For voice applications it is recommended to select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications it is recommended to select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected in the BTM2 - BTM0 bits of the backplane connection memory or LTM0 - LTM2 bits of the local connection memory as described in Table 25 on page 60 and Table 29 on page 62, respectively. 2.2.1 Variable Delay Mode The delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delays achievable in the MT90866 device are 3-channel delay, 5-channel delay, and 10-channel delay for the 2MB/s, 4MB/s, and 8MB/s respectively. The maximum delay is one frame plus three channels, one frame plus five channels, and one frame plus ten channels for the 2Mb/s, 4Mb/s and 8Mb/s modes respectively. For the backplane interface, the variable delay mode can be programmed through the backplane connection memory bits, BTM2 - BTM0. When BTM2 - BTM0 are programmed to "000", it is a per-channel variable delay from local input to the backplane output. When BTM2 - BTM0 are set to "010", it is a per-channel variable delay from backplane input to backplane output. For the local interface, the variable delay mode can be programmed through the local connection memory low bits, LTM2 - LTM0. When LTM2 - LTM0 is programmed to "000", it is a per-channel variable delay from local input to local output. When LTM2 - LTM0 is set to "010", it is a per-channel variable delay from backplane input to local output. 15 14 13 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 BBPD2 BBPD1 BBPD0 Backplane Connection Memory (BCM) 15 14 13 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 LBPD2 LBPD1 LBPD0 Local Connection Memory Low (LCML) 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Local Connection Memory High (LCMH) Figure 7 - Block Programming Data in the Connection Memories 2.2.2 Constant Delay Mode In this mode, a multiple data memory buffer is used to maintain frame integrity in all switching configurations by using three pages of Data Memory where a channel written in any of the buffers during frame N is always read out during frame N+2. For the backplane interface, when BTM2 - BTM0 is programmed to "001", it is a per-channel constant delay mode from local input to backplane output. When BTM2 - BTM0 is programmed to "011", it is a per-channel constant delay from backplane input to backplane output. For the local interface, when LTM2 - LTM0 is programmed to "001", it is a per-channel constant delay mode from local input to local output. When LTM2 - LTM0 is set to "011", it is a per-channel constant delay mode from backplane input to local output. Zarlink Semiconductor Inc. 19 MT90866 2.2.3 Microprocessor Interface Data Sheet The MT90866 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed bus structure. The required microprocessor signals are the 16-bit data bus (D15-D0), 14-bit address bus (A13-A0) and 4 control lines (CS, DS, R/W and DTA). See Figure 45, "Motorola Non-Multiplexed Bus Timing" on page 78 for the Motorola non-multiplexed bus timing. The MT90866 microprocessor port provides access to the internal registers, the connection and data memories. All locations provide read/write access except for the Local and Backplane Bit Error Rate registers (LBERR and BBERR) and Data Memory which can only be read by the users. 2.2.4 Address Mapping of Memories and Registers The address bus on the microprocessor interface selects the internal registers and memories of the MT90866. If the address bit A13 is low, then the registers are addressed by A12 to A0 as shown in Table 7 on page 20. A13 - A0 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH to 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H Control Register, CR Device Mode Selection Register, DMS Block Programming Mode Register, BPM Reserved Local Input Bit Delay Register 0, LIDR0 Local Input Bit Delay Register 0, LIDR1 Local Input Bit Delay Register 2, LIDR2 Local Input Bit Delay Register 3, LIDR3 Local Input Bit Delay Register 4, LIDR4 Local Input Bit Delay Register 5, LIDR5 Local Input Bit Delay Register 6, LIDR6 Local Input Bit Delay Register 7, LIDR7 Local Input Bit Delay Register 8, LIDR8 Local Input Bit Delay Register 9, LIDR9 Reserved Backplane Output Advancement Register 0, BOAR0 Backplane Output Advancement Register 1, BOAR1 Backplane Output Advancement Register 2, BOAR2 Backplane Output Advancement Register 3, BOAR3 Local Output Advancement Register 0, LOAR0 Local Output Advancement Register 1, LOAR1 Local Output Advancement Register 2, LOAR2 Local Output Advancement Register 3, LOAR3 Location Table 7 - Address Map For Internal Registers (A13 = 0) 20 Zarlink Semiconductor Inc. Data Sheet A13 - A0 0024H to 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH Reserved Local BER Input Selection Register, LBIS Local BER Register, LBERR Backplane BER Input Selection Register, BBIS Backplane BER Register, BBERR DPLL Operation Mode Register 1, DOM1 DPLL Operation Mode Register 2, DOM2 DPLL Output Adjustment Register, DPOA DPLL House Keeping Register, DHKR Location MT90866 Table 7 - Address Map For Internal Registers (A13 = 0) (continued) If A13 is high, the remaining address input lines are used to select the data and connection memory positions corresponding to the serial input or output data streams as shown in Table 8 on page 22. The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register (BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after system power up to establish the desired switching configuration as explained in the Frame Alignment Timing and Switching Configurations sections. The Control register is used to select Data or Connection Memory for microport operations, ST-BUS output frame and clock modes, and to set Memory Block Programing and Bit Error Rate Testing. The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits (MS2-0). The memory block programming bit allows users to program the entire connection memory in two frames (see Memory Block Programming section). The memory select bits control the selection of the connection memories or the data memories. See Table 9 on page 44 for content of the Control register. The DMS register consists of the backplane and the local mode selection bits (BMS, LG41 - LG40, LG32 - LG30, LG22 - LG20, LG12 - LG10 and LG02 - LG00) that are used to enable various switching modes for the backplane and the local interfaces respectively. See Table 10 on page 45 for the content of the DMS register. The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local connection memories in two frames (see Memory Block Programming section). If the ODE pin is low, the backplane CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin is high, all the backplane CT-Bus and local ST-BUS output drivers are controlled on a per channel basis by backplane and local connection memories, respectively. By programming BTM2 through BTM0 bits to "110" in the backplane connection memory, the user can control the per-channel input on the backplane interface. For the local interface, users can program LTM2 -0 bits to "110" in the local connection memory to control the per-channel high impedance output on the local ST-BUS. See Table 11 on page 46 for the content of the BPM register. Zarlink Semiconductor Inc. 21 MT90866 A13 (Note 1) 1 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 1 Stream Address (ST0-31) A12 0 0 0 0 0 0 0 0 0 . . . . . . 1 1 1 1 1 A11 0 0 0 0 0 0 0 0 1 . . . . . . 1 1 1 1 1 A10 0 0 0 0 1 1 1 1 0 . . . . . . 0 1 1 1 1 A9 0 0 1 1 0 0 1 1 0 . . . . . . 1 0 0 1 1 A8 0 1 0 1 0 1 0 1 0 . . . . . . 1 0 1 0 1 Stream # Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 . . . . . . Stream 27 Stream 28 Stream 29 Stream 30 Stream 31 A7 0 0 . . 0 0 0 0 . . 0 0 . . 0 0 . . 1 1 A6 0 0 . . 0 0 0 0 . . 0 0 . . 1 1 . . 1 1 A5 0 0 . . 0 0 1 1 . . 1 1 . . 1 1 . . 1 1 A4 0 0 . . 1 1 1 1 . . 1 1 . . 1 1 . . 1 1 Channel Address (Ch0-255) A3 0 0 . . 1 1 1 1 . . 1 1 . . 1 1 . . 1 1 A2 0 0 . . 1 1 1 1 . . 1 1 . . 1 1 . . 1 1 A1 0 0 . . 1 1 1 1 . . 1 1 . . 1 1 . . 1 1 A0 0 1 . . 0 1 0 1 . . 0 1 . . 0 1 . . 0 1 Data Sheet Channel # Ch 0 Ch 1 . . Ch 30 Ch 31 (Note 2) Ch 32 Ch 33 . . Ch 62 Ch 63 (Note 3 & 6) . . Ch 126 Ch 127 (Note 4 & 7) . . Ch 254 Ch 255 (Note 5) Notes: 1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers. 2. Channels 0 to 31 are used when serial stream is at 2Mb/s. 3. Channels 0 to 63 are used when serial stream is at 4Mb/s. 4. Channels 0 to 127 are used when serial stream is at 8Mb/s. 5. Channels 0 to 255 are used when serial stream is at 16Mb/s. 6. Channels 0 to 63 are used when local serial stream is in 4-bit wide sub-rate switching mode. 7. Channels 0 to 127 are used when local serial stream is in 2-bit wide sub-rate switching mode. Table 8 - Address Map for Memory Locations (A13 = 1) 2.3 Backplane Connection Memory The backplane connection memory controls the switching configuration of the backplane interface. Locations in the backplane connection memory are associated with particular STio streams. The BTM2 - 0 bits of each backplane connection memory allows the per-channel selection for the message or the connection mode, the constant or the variable delay mode, the high impedance control of the STio driver or the bit error test enable. See Table 25 on page 60 for the content per-channel control function. In the switching mode, the contents of the backplane connection memory stream address bits (BSAB4-0) and channel address bits (BCAB7-0) define the source information (stream and channel) of the time slot that will be switched to the backplane STio streams. During the message mode, only the lower 8 bits (8 least significant bits) of the backplane connection memory will be transferred to the STio pins. 2.4 Local Connection Memory The local connection memory controls the local interface switching configuration. Local connection memory is split into a high and a low part. Locations in the local connection memory are associated with particular STo output streams. The LTM2 - 0 bits of each local connection memory low allows the per-channel selection for the message or the connection mode, the constant or the variable delay mode, the high impedance control of the STo driver or the bit error test enable. See Table 29 on page 62 for the content per-channel control function. 22 Zarlink Semiconductor Inc. Data Sheet MT90866 In the switching mode, the contents of the local connection memory low stream address bits (LSAB4-0) and the channel address bits (LCAB7-0) of the local connection memory defines the source information (stream and channel) of the time slot that will be switched to the local STo streams. During the message mode, only the lower 8 bits (8 least significant bits) of the local connection memory low bits are transferred to the STo pins. In the sub-rate switching mode, although the output channels are divided up into 2 or 4-bit channels, the input streams still have 8-bit channel boundaries. Therefore, it is necessary to indicate which bits in the input 8-bit channel will be switched out to the 2 or 4-bit channel. When 2-bit or 4-bit sub-rate switching is enabled, the LSRS1-0 bits in the local connection memory high define which bit positions contains the sub-rate data. 2.5 DTA Data Transfer Acknowledgment Pin The DTA pin of the microprocessor is driven LOW by internal logic to indicate that a data bus transfer is completed. When the bus cycle ends, this pin switches to the high impedance state. An external pull-up of between 1K and 10K is required at this output. 2.6 Bit Error Rate Test The MT90866 offers users a Bit Error Rate (BER) test feature for the backplane and the local interfaces. The circuitry of the BER test consists of a transmitter and a receiver on both interfaces that can transmit and receive the BER patterns independently. The transmitter can output a pseudo random patterns of the form 215 - 1 to any channel and any stream within a frame time. For the test, users can program the output channel and stream through the backplane or local connection memory and the input channel and stream using Local or Backplane BER Input Selection (BIS) registers. See Table 16 on page 52 and Table 18 on page 52 for the LBIS and the BBIS registers contents, respectively. The receiver receives the BER pattern and does an internal BER pattern comparison. For backplane interface, the comparison result is stored in the Backplane BER register (BBERR). For local interface, the result is stored in the Local BER register (LBERR). 2.7 External Tristate Control The MT90866 has the flexibility to provide users with the choice of external per-channel tristate control. Two control signals are provided. For the backplane interface, it is the BCSTo output. For the local interface, it is the LCSTo output. Each control signal has a data rate of 32.768Mb/s with 4,096 control bits per frame. Each bit position corresponds to a specific output stream and channel location. When the control bit is high, the corresponding output channel is in the high impedance state, whereas when the control bit is low, the corresponding output channel has active output data. 2.7.1 BCSTo Control Stream When the STio0-31 streams are in the 8Mb/s mode, the STio0_Ch0 control bit of the BCSTo stream is advanced by thirty-six C32/64o 32.768 Mb/s clock cycles from the backplane frame boundary. See Figure 8, "Backplane Control (BCSTo) Timing when the STio data rate is 8Mb/s" on page 24 for the BCSTo control bit pattern. When the STio0-15 streams are in the 16Mb/s mode, the STio0_Ch0 control bit of the BCSTo is advanced by thirty-six C32/64o 32.768 Mb/s clock cycles from the backplane frame boundary. See Figure 9, "Backplane Control (BCSTo) Timing when the STio data rate is 16Mb/s" on page 24 for the BCSTo control bit pattern. Zarlink Semiconductor Inc. 23 MT90866 Frame Boundary C8_A_io, C8_B_io c32o Thirty-six c32o cycles STio26,Ch125 STio27,Ch125 STio28,Ch125 STio29,Ch125 STio30,Ch126 STio31,Ch127 STio0,Ch0 STio1,Ch0 STio2,Ch0 STio3,Ch0 Data Sheet Frame Boundary BCSTo0 (8Mb/s Mode) Figure 8 - Backplane Control (BCSTo) Timing when the STio data rate is 8Mb/s Frame Boundary C8_A_io, CA_B_io c32o Thirty-six c32o cycles STio10,Ch250 STio11,Ch251 STio12,Ch252 STio13,Ch253 STio14,Ch254 STio15,Ch255 STio0,Ch0 STio1,Ch0 STio2,Ch0 STio3,Ch0 BCSTo0 (16Mb/s Mode) Figure 9 - Backplane Control (BCSTo) Timing when the STio data rate is 16Mb/s 2.7.2 LCSTo Control Stream The LCSTo control bits are partitioned into 128 time slots, Slots 0 to 127. Each slot has 32 bits. Dummy bits represent logic levels which should be ignored by the users. The first control bit in Slot 0 is advanced by thirty-two C32/64o 32.768 Mb/s clock cycles from the frame boundary. See Figure 10, "Local Control (LCSTo) Timing when STo0-18 are operated at 8Mb/s" on page 25 for the partition of the time slots and the frame alignment details. When the STo0-18 streams are operated at 8Mb/s, Slots 0 to 127 are used to represent the control bits for Channels 0 to 127 of the 8Mb/s streams. See Figure 10, "Local Control (LCSTo) Timing when STo0-18 are operated at 8Mb/s" on page 25 for the LCSTo control bit pattern. When the STo0-18 streams are operated at 4Mb/s, Slots 2N (where N = 0 to 63) have the control bit pattern but Slots 2N+1 have dummy bits which should be ignored by the user. See Figure 11, "Local Control (LCSTo) Timing when STo0-18 are operated at 4Mb/s" on page 26 for the LCSTo control bit pattern. When the STo0-27 streams are operated at 2Mb/s, Slots 4N (where N = 0 to 31) have the control bit pattern, but Slots 4N+1, 4N+2 and 4N+3 have dummy bits. See Figure 12, "Local Control (LCSTo) Timing when all STo0-27 are operated at 2Mb/s" on page 27 for the LCSTo control bit pattern. When the STo streams are programmed with various data rates as described in Table 6 on page 18, the available control bit positions in every time slot is associated with the corresponding output stream channels which operate at various data rates. Figure 13, "Example of Local Control (LCSTo) Timing when the Local Streams have Different Data Rates" on page 28 gives an example when STo0-3, 4-7, 8-11, 12-15, 16-27 are programmed to operate at 8Mb/s, 4Mb/s, 8Mb/s, 4Mb/s and 2Mb/s respectively. 24 Zarlink Semiconductor Inc. STio6,Ch1 STio7,Ch1 STio8,Ch1 STio9,Ch1 STio10,Ch1 STio11,Ch1 STio12,Ch1 STio13,CH1 STio14,Ch1 STio15,Ch1 STio0,Ch2 STio1,Ch2 STio2,Ch2 STio3,Ch2 STio4,Ch2 STio5,Ch2 STio6,Ch2 STio7,Ch2 STio0,Ch2 STio1,Ch2 STio2,Ch2 STio3,Ch2 STio4,Ch2 STio5,Ch2 STio6,Ch2 STio7,Ch2 STio22,Ch0 STio23,Ch0 STio24,Ch0 STio25,Ch0 STio26,Ch0 STio27,Ch0 STio28,Ch0 STio29,CH0 STio30,Ch0 STio31,Ch0 STio0,Ch1 STio1,Ch1 STio2,Ch1 STio3,Ch1 STio4,Ch1 STio5,Ch1 STio6,Ch1 STio7,Ch1 STio0,Ch1 STio1,Ch1 STio2,Ch1 STio3,Ch1 STio4,Ch1 STio5,Ch1 STio6,Ch1 STio7,Ch1 Frame Boundary Ch2 STo0 Ch2 STo1 Ch2 STo2 Ch2 STo3 Ch2 STo4 Ch2 STo5 Ch2 STo6 Ch2 STo7 Ch2 STo8 Ch2 STo9 Ch2 STo10 Ch2 STo11 Ch2 STo12 Ch2 STo13 Ch2 STo14 Ch2 STo15 Ch2 STo16 Ch2 STo17 Ch2 STo18 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch3 STo0 Ch3 STo1 Ch3 STo2 Ch3 STo3 Ch3 STo4 Ch3 STo5 Ch3 STo6 Ch3 STo7 Ch3 STo8 Ch3 STo9 Ch3 STo10 Ch3 STo11 Ch3 STo12 Ch3 STo13 Ch3 STo14 Ch3 STo15 Ch3 STo16 Ch3 STo17 Ch3 STo18 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Data Sheet Zarlink Semiconductor Inc. 8Mb/s MT90866 25 8Mb/s LCSTo0 Slot 127 Frame Boundary Slot 0 Thirty-two c32o cycles Slot 0 Slot 2 Slot 3 Slot 1 Frame Boundary Slot 2 Slot 3 Slot 4 Slot 1 Figure 10 - Local Control (LCSTo) Timing when STo0-18 are operated at 8Mb/s Ch0 STo0 Ch0 STo1 Ch0 STo2 Ch0 STo3 Ch0 STo4 Ch0 STo5 Ch0 STo6 Ch0 STo7 Ch0 STo8 Ch0 STo9 Ch0 STo10 Ch0 STo11 Ch0 STo12 Ch0 STo13 Ch0 STo14 Ch0 STo15 Ch0 STo16 Ch0 STo17 Ch0 STo18 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch1 STo0 Ch1 STo1 Ch1 STo2 Ch1 STo3 Ch1 STo4 Ch1 STo5 Ch1 STo6 Ch1 STo7 Ch1 STo8 Ch1 STo9 Ch1 STo10 Ch1 STo11 Ch1 STo12 Ch1 STo13 Ch1 STo14 Ch1 STo15 Ch1 STo16 Ch1 STo17 Ch1 STo18 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Frame Boundary Slot 0 Ch1 STo0 Ch1 STo1 Ch1 STo2 Ch1 STo3 Ch1 STo4 Ch1 STo5 Ch1 STo6 Ch1 STo7 Ch1 STo8 Ch1 STo9 Ch1 STo10 Ch1 STo11 Ch1 STo12 Ch1 STo13 Ch1 STo14 Ch1 STo15 Ch1 STo16 Ch1 STo17 Ch1 STo18 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch0 STo0 Ch0 STo1 Ch0 STo2 Ch0 STo3 Ch0 STo4 Ch0 STo5 Ch0 STo6 Ch0 STo7 Ch0 STo8 Ch0 STo9 Ch0 STo10 Ch0 STo11 Ch0 STo12 Ch0 STo13 Ch0 STo14 Ch0 STo15 Ch0 STo16 Ch0 STo17 Ch0 STo18 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit 26 LCSTo0 Slot 127 MT90866 Zarlink Semiconductor Inc. 4Mb/s 4Mb/s Frame Boundary Slot 0 Thirty-two c32o cycles Slot 0 Slot 2 Slot 3 Slot 1 Frame Boundary Slot 2 Slot 3 Slot 4 Slot 1 Data Sheet Figure 11 - Local Control (LCSTo) Timing when STo0-18 are operated at 4Mb/s Frame Boundary Slot 0 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Data Sheet Zarlink Semiconductor Inc. 2Mb/s MT90866 27 2Mb/s LCSTo0 Slot 127 Frame Boundary Slot 0 Thirty-two c32o cycles Slot 0 Slot 2 Slot 3 Slot 1 Frame Boundary Slot 2 Slot 3 Slot 4 Slot 1 Figure 12 - Local Control (LCSTo) Timing when all STo0-27 are operated at 2Mb/s Ch0 STo0 Ch0 STo1 Ch0 STo2 Ch0 STo3 Ch0 STo4 Ch0 STo5 Ch0 STo6 Ch0 STo7 Ch0 STo8 Ch0 STo9 Ch0 STo10 Ch0 STo11 Ch0 STo12 Ch0 STo13 Ch0 STo14 Ch0 STo15 Ch0 STo16 Ch0 STo17 Ch0 STo18 Ch0 STo19 Ch0 ST020 Ch0 STo21 Ch0 STo22 Ch0 STo23 Ch0 STo24 Ch0 STo25 Ch0 STo26 Ch0 STo27 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Frame Boundary Slot 0 This drawing is used to illustrate the LCSTo control bit format with a specific data rate combination from different local data streams. For this drawing, we assume that LSTo0-3, 4-7, 8-11, 12-15, 16-27 have data rates of 8Mb/s, 4Mb/s, 8Mb/s, 4Mb/s and 2Mb/s respectively. Ch2 STo0 Ch2 STo1 Ch2 STo2 Ch2 STo3 Ch1 STo4 Ch1 STo5 Ch1 STo6 Ch1 STo7 Ch2 STo8 Ch2 STo9 Ch2 STo10 Ch2 STo11 Ch1 STo12 Ch1 STo13 Ch1 STo14 Ch1 STo15 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch3 STo0 Ch3 STo1 Ch3 STo2 Ch3 STo3 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch3 STo8 Ch3 STo9 Ch3 STo10 Ch3 STo11 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch0 STo0 Ch0 STo1 Ch0 STo2 Ch0 STo3 Ch0 STo4 Ch0 STo5 Ch0 STo6 Ch0 STo7 Ch0 STo8 Ch0 STo9 Ch0 STo10 Ch0 STo11 Ch0 STo12 Ch0 STo13 Ch0 STo14 Ch0 STo15 Ch0 STo16 Ch0 STo17 Ch0 STo18 Ch0 STo19 Ch0 ST020 Ch0 STo21 Ch0 STo22 Ch0 STo23 Ch0 STo24 Ch0 STo25 Ch0 STo26 Ch0 STo27 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch1 STo0 Ch1 STo1 Ch1 STo2 Ch1 STo3 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Ch1 STo8 Ch1 STo9 Ch1 STo10 Ch1 STo11 Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit Dummy Bit 28 LCSTo0 Slot 127 MT90866 Zarlink Semiconductor Inc. (8Mb/s) (8Mb/s) (4Mb/s) (8Mb/s) (4Mb/s) (2Mb/s) (8Mb/s) (4Mb/s) (8Mb/s) (4Mb/s) (2Mb/s) (4Mb/s) (8Mb/s) (4Mb/s) Frame Boundary Slot 0 Thirty-two c32o cycles Slot 0 Slot 2 (2Mb/s) (8Mb/s) (4Mb/s) (8Mb/s) (4Mb/s) Slot 3 (2Mb/s) Slot 1 Frame Boundary Slot 2 Slot 3 Slot 4 Slot 1 Data Sheet Figure 13 - Example of Local Control (LCSTo) Timing when the Local Streams have Different Data Rates Frame Boundary Slot 0 Data Sheet 2.8 DPLL MT90866 The Digital Phase Locked Loop (DPLL) accepts selectable 1.544MHz, 2.048MHz, or 8kHz input reference signals. It accepts reference inputs from independent sources and provides bit-error-free reference switching. The DPLL meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard. The DPLL also provides the timing for the rest of the MT90866 Digital Switch, generating several network clocks with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the requirements of the H.110 clock specification. The master clock (CLK80M) for the DPLL is provided by the Analog Phase Locked Loop (APLL) from the MT90866 master clock input pin C20i. Since the APLL output is "locked" to the input, the accuracy of CLK80M clock is equal to the accuracy of C20i. 2.9 MT90866 Modes of Operation The DPLL, and consequently the MT90866, can, as required by the H.110 standard, operate in three different modes: Primary Master, Secondary Master and Slave. See Figure 14, "Typical Timing Control Configuration" on page 29. To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 20 on page 53 and Table 21, "DPLL Operation Mode (DOM2) Register Bits" on page 56 for the contents of these registers. In all modes the MT90866 monitors both the "A Clocks" (C8_A_io and FRAME_A_io) and the "B Clocks" (C8_B_io and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the "A Clocks" and "B Clocks" respectively. CT_C8_A/CT_FRAME_A CT_C8_B/CT_FRAME_B CT_NETREF1 CT_NETREF2 NREFo A_Clocks B_Clocks CTREF1 A_Clocks B_Clocks CTREF2 CTREF1 CTREF2 A_Clocks B_Clocks A_Clocks LREF0-7 PRIMARY MASTER Network Ref (8kHz / T1 / E1) LREF0-7 SECONDARY MASTER Network Ref (8kHz / T1 / E1) LREF0-7 SLAVE LREF0-7 SLAVE Network Ref (8kHz / T1 / E1) Network Ref (8kHz / T1 / E1) Figure 14 - Typical Timing Control Configuration B_Clocks NREFo Zarlink Semiconductor Inc. 29 MT90866 2.9.1 Primary Master Mode Data Sheet In the Primary Master Mode, the MT90866 drives the "A Clocks" (C8_A_io and FRAME_A_io), by locking to the primary reference (PRI_REF). The PRI_REF can be provided by one of the locally derived network reference sources (LREF0-7), or the CTREF1 input or the CTREF2 input. In this mode the MT90866 has the ability to monitor the primary reference. If the primary reference becomes unreliable, the device continues driving "A Clocks" in stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference (SEC_REF) for its network timing. The secondary reference can be provided by one of the local network references (LREF0-7), the CTREF1 or the CTREF2. If the primary reference comes back or recovers, the MT90866 makes a Stratum 4 Enhanced compatible switch back to the original primary reference and the system returns to normal operation state. If necessary, the MT90866 can be prevented from switching back to the original primary reference by programming the RPS bit in DOM1 register to give preference to the secondary reference. While in the Primary Master mode, the MT90866 attenuates jitter and wander above 1.52 Hz from the selected input reference clock and generates all output clocks according to the DPLL jitter transfer function diagram on Figure 19, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on page 40 and Figure 20, "Detailed DPLL Jitter Transfer Function Diagram" on page 40. For the Primary Master mode selection, see Table 22, "MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers" on page 58. 2.9.2 Secondary Master Mode In the Secondary Master Mode, the MT90866 drives the "B Clocks" (C8_B_io and FRAME_B_io), by locking to the "A Clocks". As required by the H.110 standard, the "B Clocks" are edge-synchronous with the "A Clocks", as long as jitter on the "A Clocks" meets Telcordia GR-1244-CORE specifications. If the "A Clocks" become unreliable, system software is notified and the MT90866 continues driving the "B Clocks" in stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference (SEC_REF) for its network timing. The secondary reference can be the local network reference (LREF0-7), the CTREF1 or the CTREF2. If the "A Clocks" can not recover, the designated secondary master can be promoted to primary master by system software. This promotion will cause the "B Clocks" to assume the role of the "A Clocks". For the Secondary Master mode selection, see Table 22, "MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers" on page 58. 2.9.3 Slave Mode In the Slave Mode, the MT90866 is phase locked to the "A Clocks". If the "A Clocks" become unreliable, the device goes to stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the "B Clocks". The MT90866 will perform all required functionality as long as the "A Clocks" and the "B Clocks" conform to the Telcordia GR-1244-CORE jitter specifications. In addition, the device can be used to generate a CT reference (CT_REF1 or CT_REF2) from its network references, LREF0-7. While the device is in Slave Mode and the "A Clocks" or the "B Clocks" do not recover, then the designated slave can be promoted to secondary master by system software. In that case, the network reference can be used as the secondary reference. Table 22 on page 58 shows how to program the DOM1 and DOM2 registers to enable the Slave mode of the MT90866. 30 Zarlink Semiconductor Inc. Data Sheet 2.10 DPLL Functional Description HOLDOVER_RESET (HRST bit in DOM2) (POS0-6 bits in DPOA) MT90866 PHASE_OFFSET MTIE_RESET (MRST bit in DOM2) SKEW_CONTROL REF_SEL PRI MUX LOS_PRI (SK0-2 bits in DPOA) (RPS bit in DOM1) PRI_LOS Pin C64 HOLDOVER MTIE_START MTIE_DONE (Selected by FDM0-1 bits in DOM2) AUTODETECT SEC_LOS Pin State Machine (Fig 16) SEC MUX LOS_SEC CT_C8 (C8_A_o) PLL (Fig 17) (C8_B_o) C1M5o CT_FRAME (FRAME_A_o) or or REF_SELECT FREQ_MOD_PRI (FP0-1 bits in DOM1) (FRAME_B_o) Frequency FREQ_MOD_SEC (FS0-1 bits in DOM1) Mode MUX FREQ_MOD PRI_REF (Selected by SP0-3 bits in DOM1) SEC_REF (Selected by SS0-3 bits in DOM1) Reference Select MUX REF FRAME FAIL_PRI Reference Monitor C8_A_i FRAME_A_i FRAME_B_i Frame Select MUX CT Clock and Frame Monitor FAIL_A CLK80M Reference FAIL_SEC Monitor C8_B_i CT Clock and Frame Monitor FAIL_B C20i APLL Figure 15 - DPLL Functional Block Diagram 2.10.1 Reference Select and Frequency Mode MUX Circuits The DPLL accepts two simultaneous reference input signals and operates on their rising edges. Either the primary reference (PRI_REF) signal or the secondary reference (SEC_REF) signal can be selected to be the reference signal (REF) to the PLL circuit. The appropriate frequency mode input (either FREQ_MOD_PRI or FREQ_MOD_SEC) is selected to be the input of the PLL Circuit. The selection is done by the State Machine Circuit based on the current state. The FREQ_MOD_PRI and the FREQ_MOD_SEC are 2-bit wide inputs which reflect the value in the FP1-0 and FS1-0 bits of the DOM1 register. The primary and the secondary references operate independently from each other and can have different frequencies. Switching the reference from one frequency to another does not require the device reset to be applied. Table 20 on page 53 shows input frequency selection for the primary and secondary reference respectively. Zarlink Semiconductor Inc. 31 MT90866 2.10.2 PRI and SEC MUX Circuits Data Sheet The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1 bits of the DOM2 Register. If FDM1-0 is '10' then the Primary reference is always used regardless of failures. If FDM1-0 is '11' then the Secondary reference is always used regardless of failures. Otherwise the DPLL operates in one of two failure detection modes: Autodetect or Manual detection mode. When the FDM0 and FDM1 bits are set to low in the DOM2 register `00', the DPLL is in the Autodetect Mode. In this mode, the outputs from the Reference Monitor Circuits LOS_PRI and LOS_SEC are used by the State Machine Circuit. When the FDM0 bit is set to high and FDM1 bit is set to low `01', the DPLL is in the Manual Detection Mode and the LOS_PRI and LOS_SEC signals are selected from the PRI_LOS and SEC_LOS input pins to be used by the State Machine Circuit. See Table 21 on page 56 for selection of the Failure Detection Modes. 2.10.3 Frame Select MUX When the "A Clocks" or the "B Clocks" are selected as the input reference, an 8.192 MHz clock (either C8_A_io or C8_B_io) is provided to be the input reference to the PLL circuit (REF). Because the output frame pulse (CT_FRAME) must be aligned with the selected input frame pulse, the appropriate frame pulse (either FRAME_A_io or FRAME_B_io) is selected in the Frame Select MUX circuit to be the input of the PLL circuit (FRAME). 2.10.4 CT Clock and Frame Monitor Circuits The CT Clock and Frame Monitor circuits check the period of the C8_A_io and the C8_B_io clocks and the FRAME_A_io and FRAME_B_io frame pulses. According to the H.110 specification, the C8 period is 122 ns with a tolerance of +/- 35 ns measured between rising edges. If C8 falls outside the range of [87 ns,157 ns], the clock is rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or FAIL_B) becomes high. When the CT BUS clock and frame pulse signals return to normal, the FAIL_A or FAIL_B signal returns to logic low. 2.10.5 Reference Monitor Circuits There are two Reference Monitor Circuits: one for the primary reference (PRI_REF) and one for the secondary reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting up the appropriate fail outputs (FAIL_PRI and FAIL_SEC). These fail signals are used in the Autodetect mode as the LOS_PRI and LOS_SEC signals to indicate when the reference has failed. The method of generating a failure depends on the selected reference. When the selected reference frequency is 8.192 MHz ("A Clocks" or "B Clocks"), the fail signals are passed through from the CT Clock and Frame Monitor circuit outputs FAIL_A and FAIL_B, and used directly as FAIL_PRI and FAIL_SEC, accordingly. For all other reference frequencies (8 kHz, 1.544 MHz and 2.048 MHz), the following checks are performed: For all references, the "minimum 90 ns" check is done. This is required by the H.110 specifications - both low level and high level of the reference must last for minimum 90 ns each. - The "period in the specified range" check is done for all references. The length of the period of the selected input reference is checked if it is in the specified range. For the E1 (2.048 MHz clock) or the T1 (1.544 MHz clock) reference, the period of the clock can vary within the range of 1 +/- 1/4 of the defined clock period which is 488 ns for the E1 clock and 648 ns for T1 clock. For the 8KHz reference, the variation is from 1 +/1/32 period. - If the selected reference is E1 or T1, "64 periods in the specified range" check is done. The selected reference is observed for a long period (64 reference clock cycles) and checked if it is within the specified range - from 62 to 66 clock periods. These reference signal verifications include a complete loss or a large frequency shift of the selected reference signal. When the reference signal returns to normal, the LOS_PRI and LOS_SEC signals will return to logic low. - 32 Zarlink Semiconductor Inc. Data Sheet 2.10.6 State Machine Circuit MT90866 The State Machine handles the reference selection. Depending on REF_SEL and LOS signals (selection between FAIL_PRI and PRI_LOS and between FAIL_SEC and SEC_LOS), the state machine selects PRI_REF or SEC_REF as the current input reference and dictates the PLL Circuit mode: Normal or Holdover Mode. In the Normal Mode, the DPLL output clocks are locked to the selected input reference (PRI_REF or SEC_REF). In the Holdover Mode, the DPLL clocks retain the phase and frequency values they had 32 to 64 ms prior to moving from the Normal to the Holdover Mode. When going from the Holdover to the Normal Mode, the State Machine activates the MTIE circuit and goes through the states MTIE PRI or MTIE SEC to prevent a phase shift of the output clocks during the DPLL reference switch (from PRI_REF to SEC_REF and vice versa). The state diagram is given in Figure 16, "State Machine Diagram" on page 33. RESET Pin = 0 and xx0 Normal PRI 0 Normal SEC 4 RESET Pin = 0 and xx1 0X0 or 011 1XX or X01 MTIE PRI 1X0 or X01 0x0 or 011 Holdover PRI 100 or x01 2 3 100 or X01 0X0 or X1X MTIE SEC 100 or X01 7 0x0 or X11 0x0 or 011 Holdover SEC 6 XXX = {LOS_PRI, LOS_SEC, REF_SEL} Figure 16 - State Machine Diagram Zarlink Semiconductor Inc. 33 MT90866 2.10.7 Phase Locked Loop (PLL) Circuit Data Sheet As shown in Figure 17, "Block Diagram of the PLL Module" on page 34, the PLL module consists of a Skew Control, Maximum Time Interval Error (MTIE), Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop Filter, Digitally Controlled Oscillator (DCO), Divider and Frequency Select MUX modules. HOLDOVER_RESET HOLDOVER PHASE_OFFSET REF C64 MTIE_RESET SKEW_CONTROL Skew Control (Fig 18) REF_VIR MTIE MTIE_DONE MTIE_START Phase Detector Phase Offset Adder Phase Slope Limiter Loop Filter CT_C8 DCO Divider C2M C1M5o CT_FRAME FRAME FREQ_MOD FEEDBACK Frequency Select MUX Figure 17 - Block Diagram of the PLL Module 2.10.7.1 Skew Control The circuit delays a selected reference input with a tapped delay line with seven taps - see Figure 18, "Skew Control Circuit Diagram" on page 34. The maximum delay of the per unit delay element is factored at intervals of 3.5ns. The tap is selected by the SKEW_CONTROL bus which is programmed by the SKC2-SKC0 bits of the DPLL Output Adjustment (DPOA) register. The skew of this input will result in a static phase offset which varies from 0 to 7 steps of the maximum delay per unit delay element, between the input and the outputs of the DPLL. reference input SKEW_CONTROL Figure 18 - Skew Control Circuit Diagram 2.10.7.2 Maximum Time Interval Error (MTIE) The MTIE circuit prevents any significant change in the output clock phase during a reference switch. Because the input references can have any relationship between their phases and the output follows the selected input reference, any switch from one reference to another could cause a large phase jump in the output clock if such a circuit did not exist. This large phase jump could cause significant data loss. The MTIE circuit keeps the phase difference between the output clock of the DPLL and the input reference the same as if the reference switch had not taken place. 34 Zarlink Semiconductor Inc. MUX delayed reference Data Sheet The MTIE circuit has two modes: - MT90866 - Measuring mode - the circuit measures the phase difference between the new reference from the Skew Control circuit and the feedback signal (FEEDBACK) from the Frequency Select MUX circuit. This mode is active during the movement of the DPLL from the Holdover to the Normal Mode, and is set by the MTIE_START signal of the State machine module. The measured value is stored into a counter and used in the Delay mode. When the measurement process is done, the State Machine module is notified by generating the MTIE_DONE signal, allowing it to go to the Normal Mode. Delay mode - after the rising edge of the new reference clock from the Skew Control circuit, the MTIE circuit uses the measured value to generate the virtual reference pulse (REF_VIR) to the Phase Detector circuit. While the DPLL is in the Normal Mode, the MTIE Circuit is in Delay mode. It keeps the phase difference between the output signals of the DPLL and selected input reference as the previous output signal would have been if the reference switch had not taken place. During a reference switch, the State Machine module first changes the mode of the DPLL from the Normal to the Holdover Mode. In the Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates very accurate outputs using storage techniques. Because the input reference coming from the Skew Control circuit is asynchronous to the sampling clock used in the MTIE circuit, a phase error may exist between the selected input reference signal and the output signal of the DPLL. In the worst case, the Maximum Time Interval Error (MTIE) is one period of the internally used clock cycle (65.536 MHz if the selected reference frequency is 8 kHz, 2.048 MHz and 8.192 MHz, and 49.408 MHz when the selected reference frequency is 1.544 MHz). This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between the input signal and the output signal can change. The value of this delay is the accumulation of the error measured during each reference switch. After many switches from one reference to another, the delay between the selected input reference and the DPLL output clocks can become unacceptably large. The user should provide MTIE reset (set MRST bit in the DOM2 register to high) causing output clocks to align to the nearest edge of the selected input reference. 2.10.7.3 Phase Detector The Phase Detector circuit compares the virtual reference signal from the MTIE Circuit (REF_VIR) with the feedback signal from the Frequency Select MUX circuit (FEEDBACK) with respect to their rising edges, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Phase Offset Adder Circuit. The Frequency Select MUX allows the proper feedback signal to be selected (e.g. 8kHz, 1.544MHz, 2.048MHz or 8.192MHz). 2.10.7.4 Phase Offset Adder The Phase Offset Adder Circuit adds the PHASE_OFFSET word (bits POS6-POS0 of the DPLL Output Adjustment register - see Table 23 on page 59) to the error signal from the Phase Detector circuit to create the final phase error. This value is passed to the Phase Slope Limiter circuit. The PHASE_OFFSET word can be positive or negative. Since the PLL will stabilize to a situation where the average of the sum of the phase offset word and the phase detector output is zero, a nonzero value in the input of the Phase Offset Adder circuit will result in a static phase offset between the input and output signals of the DPLL. If the selected input reference of the DPLL is either 8KHz or 2.048 MHz, the step size in this static phase offset is 15.2ns. With a 7-bit 2's complement value, the static phase offset can be set between -0.96s and +0.97s. If the selected input reference of the DPLL is 1.544 MHz, the maximum phase offset is between -1.27s and 1.29s with a resolution of 20.2ns. Together with the Skew Control bits (SKC2-SKC0), users can program a static phase offset between -960 ns and +990 ns if the selected input reference of the DPLL is either 8kHz or 2.048MHz. If the selected reference is 1.544MHz, the programmable phase offset is between -1.27s and 1.30s. For the programmable ranges mentioned above, the resolution is 1.9 ns per step. See Table 23 on page 59 for the content of the DPOA register. Zarlink Semiconductor Inc. 35 MT90866 Data Sheet When the selected input reference frequency of the DPLL is 8.192 MHz ("A Clocks" or "B Clocks" are selected as the reference), the Phase Offset Adder is bypassed. The output of the Phase Detector circuit is connected directly to the input of the Phase Slope Limiter circuit. When an 8.192 MHz clock (C8_A_io or C8_B_io) is used as the reference in the Secondary Master or the Slave mode, the H.110 standard requires the output clock to always follow the input reference on an edge-to-edge basis, so the static phase offset is not required. 2.10.7.5 Phase Slope Limiter The limiter receives the error signal from the Phase Offset Adder circuit and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 7.6 ns per 125us. Because of this slope, the MT90866 is within the maximum phase slope of 81 ns per 1.326ms specified by the Telcordia GR-1244-CORE standard. The frequency stability of the Holdover Mode is 0.07 ppm, which translates to a worst case 49 frame (125s) slips in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of 0.37 ppm (255 frame slips per 24 hours). 2.10.7.6 Loop Filter The Loop Filter circuit gives frequency offset to the DCO circuit, based on the phase difference between the input and the feedback reference. It is similar to a first order low pass filter, with two positions for cut-off frequency (-3dB attenuation) depending on the selected reference frequency, and it mainly determines the jitter transfer function of the DPLL. In Primary Master mode when the selected input reference frequency is either 2.048 MHz, 1.544 MHz or 8 kHz, the cut-off frequency is approximately at 1.52Hz and all the reference variations, including jitter, are attenuated according to the DPLL jitter transfer function (see Figure 19, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on page 40 and Figure 20, "Detailed DPLL Jitter Transfer Function Diagram" on page 40). The Loop Filter circuit ensures that the jitter transfer requirements in ETS 300-011 and Telecordia GR-499-CORE are met when the selected reference frequency is either 2.048 MHz, 1.544 MHz or 8 kHz. When the selected input reference frequency is 8.192 MHz (i.e. in Secondary Master or Slave modes), the reference variations are bypassed to the output clocks. The cut-off frequency is well beyond 500Hz, the corner frequency of the Telcordia GR-1244-CORE input jitter tolerance curve. The storage techniques, which enable generating very accurate output frequencies during the Holdover Mode of DPLL, are built into the Loop Filter circuit. When no jitter is presented on the selected input reference, the holdover frequency stability is 0.007 ppm. 2.10.7.7 Digitally Controlled Oscillator (DCO) The DCO circuit adds frequency offset from the Loop Filter, which represents the phase error between the input and the feedback reference, to the ideal center frequency value and generates appropriately corrected output high speed clock. The Synchronization method of the DCO is dependent on the state of the DPLL State Machine module. In the Normal Mode, the DCO circuit provides an output signal which is frequency and phase locked to the selected input reference signal. In the Holdover Mode, the DCO circuit is running at a frequency that is equal to the frequency which was generated by the DCO circuit when the DPLL was in the Normal Mode. In the Freerun Mode, the DCO circuit is free running at its center frequency with an output accuracy equal to the accuracy of the device master clock (C20i). The DPLL intrinsic jitter of 6.25 ns (half of the DPLL master clock period) is determined by the DCO circuit. 36 Zarlink Semiconductor Inc. Data Sheet 2.10.7.8 Divider MT90866 The Divider Circuit divides the DCO output frequency down to the required outputs. The following outputs are generated: C64 (65.536 MHz clock) - used as the internal clock for the MT90866 device. CT_C8 (8.192 MHz clock), C2M (2.048 MHz clock), C1M5o (1.544 MHz clock) and CT_FRAME (8 kHz negative frame pulse) - feedback reference signals to the Frequency Select MUX Circuit. The CT_FRAME and the CT_C8 are required clocks. C1M5o is provided as an output clock of the MT90866. The duty cycle of all output signals is independent of the duty cycle of the device master clock, C20i. The CT_C8, C2M and C1M5o clocks have nominal 50% duty cycle, The output frame pulse (CT_FRAME) is generated in such a way that it is always aligned with the CT_C8 clock to form the required H.110 CT Bus clock and frame pulse shape (when the CT_FRAME is low the rising edge of the CT_C8 defines the frame boundary). Depending on the selected input reference frequency, the CT_FRAME is generated in the following way: When the input reference frequency is 8 kHz, the output frame pulse is aligned with the rising edge of the reference. When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the output frame boundary, always keeping the described relation to the CT_C8 clock. When the reference frequency is 8.192 MHz, the output frame pulse (CT_FRAME) has to be aligned with the input frame pulse (FRAME_A_io or FRAME_B_io). Since an 8.192 MHz clock (either C8_A_io or C8_B_io) is used as the reference clock, the selected frame pulse from the Frame Select MUX is provided as the input to the Divider circuit and the CT_FRAME is synchronized to it. 2.10.7.9 Frequency Select MUX Circuit According to the selected input reference of the DPLL, this MUX will select the appropriate output frequency to be the feedback signal to the PLL and MTIE Circuits. 2.10.8 Modes of Operation The DPLL can operate in two main modes: the Normal and the Holdover Mode. Each of these modes has two states: the primary or the secondary state. The state depends on which reference is currently selected as the preferred reference the PRI_REF or the SEC_REF. When the DPLL is in the Holdover Mode and the HRST bit of the DOM2 register is pulsed logic high (or held high continuously), the DPLL operates in Freerun Mode. 2.10.8.1 Normal Mode Normal Mode is typically used when a clock source synchronized to the network is required. In the Normal Mode, the DPLL provides timing (C64, CT_C8, C2M and C1M5o) and frame synchronization (CT_FRAME) signals which are synchronized to one of two input references (PRI_REF or SEC_REF). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz, 2.048MHz or 8.192 MHz. From a device reset condition or after reference switch, the DPLL can take up to 50 seconds to phase lock the output signals to the selected input reference signal. Zarlink Semiconductor Inc. 37 MT90866 2.10.8.2 Holdover Mode Data Sheet Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted. If the FDM1-0 bits are programmed to `01' in the DOM2 register and the PRI_LOS and SEC_LOS pins are high, the DPLL is in the Holdover Mode. The DPLL can also be in the Holdover Mode if the FDM1-0 bits are programmed to `00' and the SLS and PLS bit are observed as `11' in the DPLL House Keeping Register (DHKR). In the Holdover Mode, the DPLL provides timing and synchronization signals which are based on storage techniques and are not locked to an external reference signal. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When the DPLL is in the Normal Mode and locks to the input reference signal, a numerical value corresponding to the DPLL output reference frequency is stored alternately in two memory locations every 32ms. When the device is switched into the Holdover Mode, the value in memory from between 32ms and 64ms is used to set the output frequency of the device. The frequency stability of the Holdover Mode is 0.07 ppm, which translates to a worst case 49 frame (125s) slips in 24 hours. Two factors affect the frequency stability of the Holdover Mode. The first factor is the drift on the frequency of the master clock (C20i) while in the Holdover Mode. Drift on the master clock directly affects the Holdover Mode stability. Note that the absolute master clock stability does not affect the Holdover Frequency stability, only the change in C20i stability while in Holdover. For example, a 32 ppm master clock may have a temperature coefficient of 0.1ppm/ C. So a 10 degree change in temperature, while the DPLL is in the Holdover Mode may result in an additional offset (over the 0.07 ppm) in frequency stability of 1 ppm, which is much greater than the 0.07 ppm of the DPLL. The second factor affecting Holdover frequency stability is large jitter on the reference input prior to the mode switch. 2.10.8.3 Freerun Mode When the DPLL is in the Holdover Mode and the HRST bit of the DOM2 register is pulsed logic high (or held high continuously), the device is in Freerun Mode. In Freerun Mode, the DPLL provides timing and synchronization signals which are based on the frequency of the master clock (C20i) only, and are not synchronized to the reference input signals. The frequency of the output signals is an ideal frequency with the freerun accuracy of -0.03 ppm plus the accuracy of the master clock (i.e. CT_C8 has frequency of 8.192 MHz +/- C20i_accuracy - 0.03 ppm). Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. 2.10.9 Measures of Performance The following are some the DPLL performance indicators and their corresponding definitions. 2.10.9.1 Intrinsic Output Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the applicable standards. For the DPLL, the intrinsic output jitter is determined by the master clock of the DPLL (CLK80M). The edges of the DPLL output clocks are synchronous to both edges of the master clock. That gives a resolution of 6.25 ns with an 80 MHz master clock. The intrinsic output jitter is then 6.25nsPP for all output clocks. Jitter on the master clock is transferred without attenuation to the output clocks. 38 Zarlink Semiconductor Inc. Data Sheet 2.10.9.2 Jitter Tolerance MT90866 Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards. The input jitter tolerance of the DPLL depends on the selected reference frequency and can not exceed: 15 U.I. for E1 or T1 references, and 1 U.I. for 8 kHz references. 2.10.9.3 Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. In slave and secondary master mode the H.110 standard requires the "B Clocks" to be edge-synchronous with the "A Clocks", as long as jitter on the "A Clocks" meets Telcordia GR-1244-CORE specifications. Therefore in these two modes no jitter attenuation is performed In primary master mode the jitter attenuation of the DPLL is determined by the internal 1.52Hz low pass Loop Filter and the Phase Slope Limiter. Figure 19, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on page 40 shows the DPLL jitter transfer function diagram in a wide range of frequencies, while Figure 20, "Detailed DPLL Jitter Transfer Function Diagram" on page 40 is the portion of the diagram from Figure 19 around 0dB of the jitter transfer amplitude. At this point it is possible to see that when operating in primary master mode the DPLL is a second order, type 2 PLL. The jitter transfer function can be described as a low pass filter to 1.52Hz, -20dB/decade, with peaking less then 0.5 dB. All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Since 1U.I. at 1.544MHz (648nsPP) is not equal to 1 U.I. at 2.048MHz (488nsPP). a transfer value using different input and output frequencies must be calculated in common units (e.g. seconds) as shown in the following example: What is the T1 and E1 output jitter when the T1 input jitter is 20 U.I. (T1 U.I. Units) and the T1 to T1 jitter attenuation is 18 dB, for a given jittering frequency? - A ----- 20 OutputT1 = InputT1 x10 - 18 ------- 20 OutputT1 = 20 x10 = 2.5UI ( T1 ) ( 1UIT1 ) OutputE1 = OutputT1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT1 x ------------------- = 3.3UI ( T1 ) ( 488ns ) Using the method mentioned above, the jitter attenuation can be calculated for all combinations of inputs and outputs. Because intrinsic jitter is always present, the jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Zarlink Semiconductor Inc. 39 MT90866 Data Sheet Figure 19 - DPLL Jitter Transfer Function Diagram - wide range of frequencies Figure 20 - Detailed DPLL Jitter Transfer Function Diagram 40 Zarlink Semiconductor Inc. Data Sheet 2.10.9.4 Frequency Accuracy MT90866 Frequency accuracy is defined as the absolute tolerance of an output clock signal when the DPLL is not locked to an external reference, but is operating in the Freerun Mode. Because the output of the DCO Circuit has only discrete values, the output frequency of the DPLL has the limited accuracy of 0.03 ppm based upon the design implementation. In addition, the master clock (C20i) accuracy also directly affects the freerun accuracy. The freerun accuracy is then, 0.03 ppm plus the master clock accuracy. 2.10.9.5 Holdover Frequency Stability Holdover frequency stability is defined as the maximum fractional frequency offset of an output clock signal when it is operating using a stored frequency value. For the DPLL, the stored value is determined while the device is in Normal Mode and locked to an external reference signal. As a result, when the DPLL is in the Normal Mode, the stability of the master clock (C20i) does not affect the holdover frequency stability because the DPLL will compensate for master clock changes while in Normal Mode. However, when the DPLL is in the Holdover Mode, the stability of the master clock does affect the Holdover frequency stability. The holdover frequency stability is 0.07 ppm when no jitter is presented to input reference clock. 2.10.9.6 Locking Range The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to maintain the synchronization. The locking range is defined by the Loop Filter Circuit and is equal to +/- 298 ppm. Note that the locking range is related to the master clock (C20i). If the master clock is shifted by -100 ppm, the whole locking range also shifts -100 ppm downwards to be: -398ppm to 198ppm. 2.10.9.7 Phase Slope The phase slope or the phase alignment speed is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Many telecom standards like Telcordia GR-1244-CORE state that the phase slope may not exceed a certain value, usually 81ns/1.327ms (61ppm). This can be achieved by limiting the phase detector output to 61ppm or less. In the DPLL when operating in primary master mode the Phase Slope Limiter Circuit achieves the maximum phase slope to be: 56 ppm or 7.0ns/125us. When operating in secondary master or slave mode the output edges follow the input edges in accordance with the H.110 standard 2.10.9.8 Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. For the DPLL, the maximum time interval error is less then 21 ns per reference switch. 2.10.9.9 Phase Lock Time The Phase Lock Time is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input and the output signals are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) PLL loop filter iv) PLL limiter Zarlink Semiconductor Inc. 41 MT90866 Data Sheet Although a short phase lock time is desirable, it is not always possible to achieve due to other PLL requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time, but better (smaller) phase slope performance (limiter) results in longer lock times. The DPLL loop filter and limiter were optimized to meet the Telcordia GR-499-CORE jitter transfer and Telcordia GR-1244-CORE phase alignment speed requirements. Consequently, phase lock time, which is not a standards requirement, is less than 50 seconds. 2.11 Initialization of the MT90866 During power up, the TRST pin should be pulled low to ensure that the MT90866 is in the functional mode. An external pull-down resistor is required on this pin so that the MT90866 will not enter the JTAG test mode during power up. After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching matrix. This procedure prevents two serial outputs from driving the same stream simultaneously. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the switch. The memory block programming feature can also be used to quickly initialize the backplane and local connection memories. When this process is completed, the microprocessor controlling the MT90866 can bring the ODE pin high to relinquish the high impedance state control. 2.12 JTAG Support The MT90866 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller. 2.12.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the MT90866 test functions. It consists of three input pins and one output pin as follows: * Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Input (TDI) - Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Output (TDO) - Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven from an external source. * * * * 42 Zarlink Semiconductor Inc. Data Sheet 2.12.2 Instruction Register MT90866 The MT90866 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. 2.12.3 Test Data Register As specified in IEEE 1149.1, the MT90866 JTAG Interface contains three test data registers: * * The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90866 core logic. The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The Device Identification Register - The JTAG device ID for the MT90866 is 0086614BH. Version<31:28>: 0000 Part No. <27:12>: 0000 1000 0110 0110 Manufacturer ID<11:1>: 0001 0100 101 LSB<0>: 1 2.12.4 BSDL A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149 test interface. Zarlink Semiconductor Inc. 43 MT90866 3.0 Register Descriptions Read/Write Address: 0000H Data Sheet Reset Value: 0000H 15 0 14 0 13 STS3 12 STS2 11 STS1 10 STS0 9 PRST 8 CBEBB 7 SBERB 6 CBERL 5 SBERL 4 0 3 MBP 2 MS2 1 MS1 0 MS0 Bit 15-14 13-12 Name Unused STS3-2 Reserved. Description ST-BUS Frame Pulse and Clock Output Selection 1: These two bits are used to select different ST-BUS output frame pulse (ST_FPo1) and clock (ST_CKo1). STS3 0 0 1 STS2 ST_FPo1 Pulse Width 0 244ns 1 122ns 0 61ns ST_CKo1 Freq 4.096MHz 8.192MHz 16.384MHz 11-10 STS1-0 ST-BUS Frame Pulse and Clock Output Selection 0: These two bits are used to select different ST-BUS output frame pulse (ST_FPo0) and clock (ST_CKo0). STS1 0 0 1 STS0 ST_FPo0 Pulse Width 0 1 0 244ns 122ns 61ns ST_CKo0 Freq 4.096MHz 8.192MHz 16.384MHz 9 8 7 PRST CBERB SBERB PRBS Reset: When high, the PRBS transmitter output will be initialized. Backplane Bit Error Rate Clear: A low to high transition of this bit will reset the backplane internal bit error counter and the backplane BER register (BBERR). Backplane Start Bit Error Rate Test: A low to high transition in this bit starts the backplane bit error rate test. The bit error test result is kept in the backplane BER register (BBERR). Local Bit Error Rate Clear: A low to high transition of this bit will reset the local internal bit error counter and the BER register (LBERR). Local Start Bit Error Rate Test: A low to high transition in this bit starts the local bit error rate test. The bit error test result is kept in the local BER register (LBERR). Reserved. In functional mode, this bit MUST be low. Memory Block Programming: When this bit is high, the connection memory block programming feature is ready for the programming of bit 13 to bit 15 of the backplane connection memory and local connection memory low. When it is low this feature is disabled. Table 9 - Control Register (CR) Bits 6 5 4 3 CBERL SBERL Unused MBP 44 Zarlink Semiconductor Inc. Data Sheet Bit 2-0 Name MS2-0 Description MT90866 Memory Select Bits: These three bits are used to select different connection and data memories. MS2 0 0 0 0 1 MS11 0 0 1 1 0 MS0 0 1 0 1 0 Memory Selection Local Connection Memory Low Read/Write Local Connection Memory High Read/Write Backplane Connection Memory Read/Write Local Data Memory Read Backplane Data Memory Read Table 9 - Control Register (CR) Bits (continued) Read/Write Address: 0001H Reset Value: 0000H 15 0 14 BMS 13 LG41 12 LG40 11 LG32 10 LG31 9 LG30 8 LG22 7 LG21 6 LG20 5 LG12 4 LG11 3 LG10 2 LG02 1 LG01 0 LG00 Bit 15 14 Name Unused BMS Reserved. Description Backplane Mode Select: This bit refers to the different mode for the backplane interface. BMS 0 1 Switching Mode Usable Streams 8Mb/s STio0 - 31 16Mb/s STio0 - 15 13-12 LG41-LG40 Local Group 4 Mode Select: These two bits refer to different switching mode for group 4(STi16-27 and STo16-27) of the local interface. LG41 0 0 1 LG40 Switching Mode Usable Streams 0 8Mb/s STi16-18, STo16-18 1 4Mb/s STi16-18, STo16-18 0 2Mb/s STi16-27, STo16-27 11-9 LG32-LG30 Local Group 3 Mode Select: These three bits refer to different switching mode for group 3 (STi12-15 and STo12-15) of the local interface. LG32 0 0 0 0 1 LG31 0 0 1 1 0 LG30 0 1 0 1 0 Switching Mode 8Mb/s 4Mb/s 2Mb/s 4-bit wide subrate 2-bit wide subrate Usable Streams STi12-15, STo12-15 STi12-15, STo12-15 STi12-15, STo12-15 STi12-15, STo12-15 STi12-15, STo12-15 Table 10 - Device Mode Selection (DMS) Register Bits Zarlink Semiconductor Inc. 45 MT90866 Bit 8-6 Name LG22-LG20 Description Data Sheet Local Group 2 Mode Select: These three bits refer to different switching mode for group 2 (STi8-11 and STo8-11) of the local interface. LG22 0 0 0 0 1 LG21 0 0 1 1 0 LG20 0 1 0 1 0 Switching Mode 8Mb/s 4Mb/s 2Mb/s 4-bit wide subrate 2-bit wide subrate Usable Streams STi8-11, STo8-11 STi8-11, STo8-11 STi8-11, STo8-11 STi8-11, STo8-11 STi8-11, STo8-11 5-3 LG12-LG10 Local Group 1 Mode Select: These three bits refer to different switching modes for group 1 (STi4-7 and STo4-7) of the local interface. LG12 0 0 0 0 1 LG11 0 0 1 1 0 LG10 0 1 0 1 0 Switching Mode 8Mb/s 4Mb/s 2Mb/s 4-bit wide subrate 2-bit wide subrate Usable Streams STi4-7, STo4-7 STi4-7, STo4-7 STi4-7, STo4-7 STi4-7, STo4-7 STi4-7, STo4-7 2-0 LG02-LG00 Local Group 0 Mode Select: These three bits refer to different switching modes for group 0 (STi0-3 and STo0-3) of the local interface. LG02 0 0 0 0 1 LG01 0 0 1 1 0 LG00 0 1 0 1 0 Switching Mode 8Mb/s 4Mb/s 2Mb/s 4-bit wide subrate 2-bit wide subrate Usable Streams STi0-3, STo0-3 STi0-3, STo0-3 STi0-3, STo0-3 STi0-3, STo0-3 STi0-3, STo0-3 Table 10 - Device Mode Selection (DMS) Register Bits (continued) Read/Write Address: 0002H Reset Value: 0000H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 BBPD2 7 BBPD1 6 BBPD0 5 LBPD2 4 LBPD1 3 LBPD0 2 BPE 1 0 0 0 Bit 15-9 8-6 Name Unused BBPD2-0 Description Reserved. In functional mode, these bits MUST be low. Backplane Block Programming Data Bits: These bits carry the value to be loaded into the backplane connection memory block whenever the Memory Block Programming feature is activated. After the MBP bit in the control register is set to high and the BPE is set to high, the contents of the bits BBPD2 - 0 are loaded into bits 15 - 13 of the backplane connection memory. Bits 12 - 0 of the backplane connection memory are programmed to be zero. Table 11 - Block Programming Mode (BPM) Register Bits 46 Zarlink Semiconductor Inc. Data Sheet Bit 5-3 Name LBPD2-0 Description MT90866 Local Block Programming Data Bits: These bits carry the value to be loaded into the local connection memory low whenever the Memory Block Programming feature is activated. After the MBP bit in the control register is set to high and the BPE is set to high, the contents of the bits LBPD2 - 0 are loaded into bits 15 - 13 of the local connection memory low. Bits 12 - 0 of the local connection memory low and bits 15 - 0 of the local connection memory high are programmed to be zero. Block Programming Enable: A low to high transition of this bit enables the Memory Block Programming function. The BPE, BBPD2-0 and LBPD2-0 in the BPM register have to be defined in the same write operation. Once the BPE bit is set to high, MT90866 requires two frames to complete the block programming. After the block programming has finished, the BPE bit returns to low to indicate that the operation is complete. When BPE is high, BPE or MBP can be set to low to abort the programming operation. When BPE is high, the other bits in the BPM register must not be changed for two frames to ensure proper operation. Whenever the microprocessor writes BPE to be high to start the block programming function, the user must maintain the same logical value on the other bits in the BPM register to avoid any change in the setting of the device. 2 BPE 1-0 Unused Reserved. In functional mode, these bits MUST be low. Table 11 - Block Programming Mode (BPM) Register Bits (continued) Zarlink Semiconductor Inc. 47 MT90866 Read/Write Addresses: 0004H for LIDR0 register, 0006H for LIDR2 register, 0008H for LIDR4 register, 000AH for LIDR6 register, 000CH for LIDR8 register, 0005H for LIDR1 register, 0007H for LIDR3 register, 0009H for LIDR5 register, 000BH for LIDR7 register, 000DH for LIDR9 register, Data Sheet Reset Value: 0000H 15 LIDR0 0 14 LID24 13 LID23 12 LID22 11 LID21 10 LID20 9 LID14 8 LID13 7 LID12 6 LID11 5 LID10 4 LID04 3 LID03 2 LID02 1 LID01 0 LID00 LIDR1 0 LID54 LID53 LID52 LID51 LID50 LID44 LID43 LID42 LID41 LID40 LID34 LID33 LID32 LID31 LID30 LIDR2 0 LID84 LID83 LID82 LID81 LID80 LID74 LID73 LID72 LID71 LID70 LID64 LID63 LID62 LID61 LID60 LIDR3 0 LID114 LID113 LID112 LID111 LID110 LID104 LID103 LID102 LID101 LID100 LID94 LID93 LID92 LID91 LID90 LIDR4 0 LID144 LID143 LID142 LID141 LID140 LID134 LID133 LID132 LID131 LID130 LID124 LID123 LID122 LID121 LID120 LIDR5 0 LID174 LID173 LID172 LID171 LID170 LID164 LID163 LID162 LID161 LID160 LID154 LID153 LID152 LID151 LID150 LIDR6 0 LID204 LID203 LID202 LID201 LID200 LID194 LID193 LID192 LID191 LID190 LID184 LID183 LID182 LID181 LID180 LIDR7 0 LID234 LID233 LID232 LID231 LID230 LID224 LID223 LID222 LID221 LID220 LID214 LID213 LID212 LID211 LID210 LIDR8 0 LID264 LID263 LID262 LID261 LID260 LID254 LID253 LID252 LID251 LID250 LID244 LID243 LID242 LID241 LID240 LIDR9 0 0 0 0 0 0 0 0 0 0 0 LID274 LID273 LID272 LID271 LID270 Name LIDn4, LIDn3, LIDn2, LIDn1, LIDn0 (See Note 1) Description Local Input Delay Bits 4 - 0: These five bits define how long the serial interface receiver takes to recognize and to store bit 0 from the STi input pins: i.e., to start a new frame. The input delay can be selected to +7.75 data rate clock periods from the frame boundary. Note 1: n denotes an STi stream number from 0 to 27. Table 12 - Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits Corresponding Delay Bits Local Input Bit Delay LIDn4 No clock period shift (Default) + 1/4 data rate clock period + 1/2 data rate clock period + 3/4 data rate clock period 0 0 0 0 LIDn3 0 0 0 0 LIDn2 0 0 0 0 LIDn1 0 0 1 1 LIDn0 0 1 0 1 Table 13 - Local Input Bit Delay Programming 48 Zarlink Semiconductor Inc. Data Sheet Local Input Bit Delay LIDn4 + 1 data rate clock period + 1 1/4 data rate clock period + 1 1/2 data rate clock period + 1 3/4 data rate clock period + 2 data rate clock period .......... + 7 3/4 data rate clock period 1 1 0 0 0 0 0 LIDn3 0 0 0 0 1 LIDn2 1 1 1 1 0 ........... 1 1 MT90866 Corresponding Delay Bits LIDn1 0 0 1 1 0 LIDn0 0 1 0 1 0 1 Table 13 - Local Input Bit Delay Programming (continued) ST_FPo0/1 input data bit7 Bit Delay 0 LID=00000 Bit Delay 1/4 LID=00001 Bit Delay 1/2 LID=00010 Bit Delay 3/4 LID=00011 Bit Delay 1 LID=00100 Bit Delay 1 1/2 LID=00101 input data bit7 input data bit7 input data bit7 input data bit7 input data bit7 Figure 21 - Local Input Bit Delay Timing Zarlink Semiconductor Inc. 49 MT90866 Read/Write Addresses: Reset value: 15 BOAR0 BOA 71 14 BOA 70 13 BOA 61 Data Sheet 001CH for BOAR0 register, 001EH for BOAR2 register, 0000H for all BOAR registers. 12 BOA 60 11 BOA 51 10 BOA 50 9 BOA 41 8 BOA 40 7 BOA 31 001DH for BOAR1 register, 001FH for BOAR3 register, 6 BOA 30 5 BOA 21 4 BOA 20 3 BOA 11 2 BOA 10 1 BOA 01 0 BOA 00 BOAR1 BOA 151 BOA 150 BOA 141 BOA 140 BOA 131 BOA 130 BOA 121 BOA 120 BOA 111 BOA 110 BOA 101 BOA 100 BOA 91 BOA 90 BOA 81 BOA 80 BOAR2 BOA 231 BOA 230 BOA 221 BOA 220 BOA 211 BOA 210 BOA 201 BOA 200 BOA 191 BOA 190 BOA 181 BOA 180 BOA 171 BOA 170 BOA 161 BOA 160 BOAR3 BOA 311 BOA 310 BOA 301 BOA 300 BOA 291 BOA 290 BOA 281 BOA 280 BOA 271 BOA 270 BOA 271 BOA 260 BOA 251 BOA 250 BOA 241 BOA 240 Name) BOAn1, BOAn0 (See Note 1) Description Backplane Output Advancement Bits 1 - 0: These two bits represent the amount of offset that a particular stream output can be advanced. When the offset is zero, the serial output stream has normal alignment with the frame pulse. BOAn1 BOAn0 Output Advancement 0 ns 7.5 ns 15 ns 22.5 ns C8_A_io or C8_B_io period 0 - 1/16 - 1/8 - 3/16 8.192Mb/s (bit) 0 - 1/16 - 1/8 - 3/16 16.384Mb/s (bit) 0 - 1/8 - 1/4 - 3/8 0 0 1 1 0 1 0 1 Note 1: n denotes a STio stream number from 0 to 31. Table 14 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit FRAME_A_io or FRAME_B_io C64 (internal clock) 8Mb/s Stream Bit 7 advancement is 0ns BOA=00 advancement is 7.5 ns BOA=01 advancement is 15 ns BOA=10 advancement is 22.5 ns BOA=11 8Mb/s Stream 8Mb/s Stream 8Mb/s Stream Bit 7 Bit 7 Bit 7 denotes the starting point of the bit cell Figure 22 - Example of Backplane Output Advancement Timing 50 Zarlink Semiconductor Inc. Data Sheet Read/Write Addresses: Reset value: 15 14 13 12 11 MT90866 0020H for LOAR0 register, 0022H for LOAR2 register, 0000H for all LOAR registers. 10 9 8 7 6 5 0021H for LOAR1 register, 0023H for LOAR3 register, 4 3 2 1 0 LOAR0 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA 71 70 61 60 51 50 41 40 31 30 21 20 11 10 01 00 LOAR1 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA 151 150 141 140 131 130 121 120 111 110 101 100 91 90 81 80 LOAR2 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA 231 230 221 220 211 210 201 200 191 190 181 180 171 170 161 160 LOAR3 0 0 0 0 0 0 0 0 LOA LOA LOA LOA LOA LOA LOA LOA 271 270 271 260 251 250 241 240 Name LOAn1, LOAn0 (See Note 1) Description Local Output Advancement Bits 1-0: These two bits represent the amount of offset that a particular stream output can be advanced. When the offset is zero, the serial output stream has normal alignment with the frame pulse. LOAn1 LOAn0 Output Advancement 0 ns - 7.5 ns - 15 ns - 22.5 ns C8_A_io or C8_B_io period 0 - 1/16 - 1/8 - 3/16 2.048Mb/s (bit) 0 - 1/64 - 1/32 - 3/64 4.096Mb/s (bit) 0 - 1/32 - 1/16 - 3/32 8.192Mb/s (bit) 0 - 1/16 - 1/8 - 3/16 0 0 1 1 0 1 0 1 Note 1: n denotes a STi stream number from 0 to 27. Table 15 - Local Output Advancement Registers (LOAR0 to LOAR3) Bits ST_FPo0/1 C64 (internal clock) 8Mb/s Stream Bit 7 advancement is 0 ns LOA=00 advancement is 7.5 ns LOA=01 advancement is 15 ns LOA=10 advancement is 22.5 ns LOA=11 8Mb/s Stream 8Mb/s Stream 8Mb/s Stream Bit 7 Bit 7 Bit 7 denotes the starting point of the bit cell Figure 23 - Local Output Advancement Timing 51 Zarlink Semiconductor Inc. MT90866 Read/Write Address: 0027H Reset Value: 0000H 15 0 14 0 13 0 12 LBS A4 11 LBS A3 10 LBS A2 9 LBS A1 8 LBS A0 7 LBC A7 6 LBC A6 5 LBC A5 4 LBC A4 3 LBC A3 2 LBC A2 Data Sheet 1 LBC A1 0 LBC A0 Bit 15 - 13 12 - 8 7-0 Name Unused LBSA4 - LBSA0 LBCA7 - LBCA0 Reserved. Description Local BER Input Stream Address Bits: These bits refer to the local input data stream which receives the BER data. Local BER Input Channel Address Bits: These bits refer to the local input channel which receives the BER data. Table 16 - Local Bit Error Rate Input Selection (LBIS) Register Bits Read Address: 0028H Reset Value: 0000H 15 LBER 15 14 LBER 14 13 LBER 13 12 LBER 12 11 LBER 11 10 LBER 10 9 LBER 9 8 LBER 8 7 LBER 7 6 LBER 6 5 LBER 5 4 LBER 4 3 LBER 3 2 LBER 2 1 LBER 1 0 LBER 0 Bit 15 - 0 Name LBER15 - LBER0 Description Local Bit Error Rate Count Bits: These bits refer to the local bit error counts. This counter stops incrementing when it reaches the value 0xFFFF. Table 17 - Local Bit Error Rate Register (LBERR) Bits Read/Write Address: 0029H Reset Value: 0000H 15 0 14 0 13 0 12 BBSA 4 11 BBSA 3 10 BBSA 2 9 BBSA 1 8 BBSA 0 7 BBCA 7 6 BBCA 6 5 BBCA 5 4 BBCA 4 3 BBCA 3 2 BBCA 2 1 BBCA 1 0 BBCA 0 Bit 15 - 13 12 - 8 7-0 Name Unused BBSA4 - BBSA0 BBCA7 - BBCA0 Reserved. Description Backplane BER Input Stream Address Bits: These bits refer to the backplane input data stream which receives the BER data. Backplane BER Input Channel Address Bits: These bits refer to the backplane input channel which receives the BER data. Table 18 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits 52 Zarlink Semiconductor Inc. Data Sheet Read Address: 002AH Reset Value: 0000H 15 BBER 15 14 BBER 14 13 BBER 13 12 BBER 12 11 BBER 11 10 BBER 10 9 BBER 9 8 BBER 8 7 BBER 7 6 BBER 6 5 BBER 5 4 BBER 4 3 BBER 3 2 MT90866 1 BBER 1 0 BBER 0 BBER 2 Bit 15 - 0 Name BBER15 -BBER0 Description Backplane Bit Error Rate Count Bits: These bits refer to the backplane bit error count. This counter stops incrementing when it reaches the value 0xFFFF. Table 19 - Backplane Bit Error Rate Register (BBERR) Bits Read/Write Address: 002BH for DOM1 Register Reset Value: 0000H 15 CNEN 14 BEN 13 AEN 12 RPS 11 FS1 10 FS0 9 FP1 8 FP0 7 SS3 6 SS2 5 SS1 4 SS0 3 SP3 2 SP2 1 SP1 0 SP0 Bit 15 14 Name CNEN BEN Description NREFo Output Enable Bit: When CNEN is low, NREFo output is disabled, i.e. tri-stated. When CNEN is high, NREFo output is enabled. B Clocks Output Enable Bit: When BEN is low, the "B Clocks" (C8_B_io and FRAME_B_io) are disabled, i.e. tri-stated - C8_B_io and FRAME_B_io behave as inputs. When BEN is high, the "B Clocks" are enabled - C8_B_io and FRAME_B_io behave as outputs. 13 AEN A Clocks Output Enable Bit: When AEN is low, the "A Clocks" (C8_A_io and FRAME_A_io) are disabled, i.e. tri-stated - C8_A_io and FRAME_A_io behave as inputs. When AEN is high, the "A Clocks" are enabled - C8_A_io and FRAME_A_io behave as outputs. 12 RPS Reference Selection Bit: When RPS is low, the preferred reference is the primary reference (PRI_REF). When RPS is high, the preferred reference is the secondary reference (SEC_REF). 11 - 10 FS1 - FS0 SEC_REF Frequency Selection Bits: These bits are used to select different clock frequencies for the secondary reference. FS1 0 0 1 1 FS0 0 1 0 1 Secondary Reference 8kHz 1.544MHz 2.048MHz 8.192MHz ("A Clocks" or "B Clocks") Table 20 - DPLL Operation Mode (DOM1) Register Bits Zarlink Semiconductor Inc. 53 MT90866 Bit 9-8 Name Description Data Sheet FP1 - FP0 PRI_REF Frequency Selection Bits: These bits are used to select different clock frequencies for the primary reference. FS1 0 0 1 1 FS0 0 1 0 1 Primary Reference 8kHz 1.544MHz 2.048MHz 8.192MHz ("A Clocks" or "B Clocks") 7-4 SS3 - SS0 Secondary Clock Reference Input Selection Bits: These bits are used to select secondary reference input. SS3 - SS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Secondary Clock Reference Input CTREF1 CTREF2 "A Clocks" "B Clocks" Reserved Reserved Reserved Reserved LREF0 LREF1 LREF2 LREF3 LREF4 LREF5 LREF6 LREF7 Table 20 - DPLL Operation Mode (DOM1) Register Bits (continued) 54 Zarlink Semiconductor Inc. Data Sheet Bit 3-0 Name Description MT90866 SP3 - SP0 Primary Clock Reference Input Selection Bits: These bits are used to select primary reference input. SP3 - SS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Primary Clock Reference Input CTREF1 CTREF2 "A Clocks" "B Clocks" Reserved Reserved Reserved Reserved LREF0 LREF1 LREF2 LREF3 LREF4 LREF5 LREF6 LREF7 Table 20 - DPLL Operation Mode (DOM1) Register Bits (continued) Zarlink Semiconductor Inc. 55 MT90866 Read/Write Address: 002CH for DOM2 Register Reset Value: 0000H 15 0 14 0 13 0 12 0 11 HRST 10 MRST 9 FDM1 8 FDM0 7 BFEN 6 AFEN 5 CNIN 4 DIV1 3 DIV0 2 CNS2 Data Sheet 1 CNS1 0 CNS0 Bit 15 - 12 11 Name Unused HRST Reserved. Description DPLL Hold Memory Reset Bit: When HRST is low, the DPLL hold memory circuit is in functional mode. When HRST is high, the hold memory circuit will be reset. While the DPLL is in Holdover Mode, pulsing HRST high (or holding it high continuously) will force the DPLL to the Freerun Mode. MTIE Reset Bit: When MRST is low, the DPLL MTIE circuit is in functional mode. When MRST is high, the MTIE circuit will be reset - the DPLL outputs will align with the nearest edge of the selected reference. Failure Detect Mode Bits: These two bits control how to choose the Failure Detection. FDM1 FDM0 Failure Detection Mode 10 MRST 9-8 FDM1 FDM0 0 0 1 1 0 1 0 1 Autodetect - Automatic Failure Detection by internal reference monitor circuit External - Failure Detection controlled by external inputs (PRI_LOS and SEC_LOS) Forced Primary - The DPLL is forced to use primary reference Forced Secondary - The DPLL is forced to use secondary reference 7 6 5 BFEN AFEN CNIN B Clocks Fail Output Enable Bit: When BFEN is low, FAIL_B output is disabled, i.e. tri-stated. When BFEN is high, FAIL_B output is enabled. A Clocks Fail Output Enable Bit: When AFEN is low, FAIL_A output is disabled, i.e. tri-stated. When AFEN is high, FAIL_A output is enabled. CTREF1 andCTREF2 Inputs Inverted: When CNIN is high, the CTREF1 and CTREF2 inputs will be inverted, prior to entering the DPLL module. When CNIN is low, the CTREF1 and CTREF2 inputs will not be inverted. Table 21 - DPLL Operation Mode (DOM2) Register Bits 56 Zarlink Semiconductor Inc. Data Sheet Bit 4 -3 Name DIV1 - DIV0 Description MT90866 Divider Bits: These two bits define the relationship between the input reference and the NREFo output. DIV1 0 0 1 1 DIV0 0 1 0 1 Input reference Input reference/193 (8KHz signal when input reference clock = 1.544MHz) Input reference/256 (8KHz signal when input reference clock = 2.048MHz) Reserved NREFo Output 2-0 CNS2 - CNS0 NREFo Source Selection Bits: These three bits select one of the LREF7 LREF0 to be the NREFo source. CNS2 0 0 0 0 1 1 1 1 CNS1 0 0 1 1 0 0 1 1 CNS0 0 1 0 1 0 1 0 1 NREFo Source LREF0 LREF1 LREF2 LREF3 LREF4 LREF5 LREF6 LREF7 Table 21 - DPLL Operation Mode (DOM2) Register Bits (continued) Zarlink Semiconductor Inc. 57 MT90866 Bit BEN (bit 14) AEN (bit 13) RPS (bit 12) FS1-0 (bits 11-10) Frequency of the secondary reference FP1-0 (bits 9-8) Frequency of the primary reference DOM1 register Bits SS3-0 (bits 7-4) Secondary reference selection: Data Sheet Primary Master Mode 0 - Monitor "B Clocks" 1 - Drive "A Clocks" 0 - Preferred reference is PRI_REF 00 - 8 kHz 01 - 1.544 MHz 10 - 2.048 MHz Secondary Master Mode 1 - Drive "B Clocks" 0 - Monitor "A Clocks" 0 - Preferred reference is PRI_REF 00 - 8 kHz 01 - 1.544 MHz 10 - 2.048 MHz Slave Mode 0 - Monitor "B Clocks" 0 - Monitor "A Clocks" 0 - Preferred reference is PRI_REF 11 - 8.192MHz Clock ("B Clocks") 00 - 8 kHz 01 - 1.544 MHz 10 - 2.048 MHz 11 - 8.192MHz Clock ("A Clocks") 11 - 8.192MHz Clock ("A Clocks") 0000 - CTREF1 0001 - CTREF2 1000 - LREF0 1001 - LREF1 1010 - LREF2 1011 - LREF3 1100 - LREF4 1101 - LREF5 1110 - LREF6 1111 - LREF7 0000 - CTREF1 0001 - CTREF2 1000 - LREF0 1001 - LREF1 1010 - LREF2 1011 - LREF3 1100 - LREF4 1101 - LREF5 1110 - LREF6 1111 - LREF7 0010 - Frame pulse, internally generated from "A Clocks" 0011 - Frame pulse, internally generated from "B Clocks" SP3-0 (bits 3-0) Primary reference selection: 0000 - CTREF1 0001 - CTREF2 1000 - LREF0 1001 - LREF1 1010 - LREF2 1011 - LREF3 1100 - LREF4 1101 - LREF5 1110 - LREF6 1111 - LREF7 00 - Autodetect Mode 0011 - Frame pulse, internally generated from "B Clocks" DOM 2 Register Bits FDM1, FDM0 (bits 9-8) Failure detect mode selection 00 - Autodetect Mode 01 - External Mode (Note 1) 00 - Autodetect Mode 01 - External Mode (Note 1) * Note 1: It is assumed that the switching among references is done by an external software control, if the External Mode is selected. Table 22 - MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers 58 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 002DH for DPOA Register Reset Value: 0000H 15 POS 6 14 POS 5 13 POS 4 12 POS 3 11 POS 2 10 POS 1 9 POS 0 8 0 7 0 6 0 5 0 4 0 3 0 2 MT90866 1 SKC1 0 SKC0 SKC2 Bit 15 - 9 Name POS6 - POS0 Description Phase Offset Bits: These seven bits refer to the 2's complement phase word to control the DPLL output phase offset. The offset varies in steps of 15 ns if the reference is 8kHz or 2.048MHz. The offset varies in steps of 20 ns if the reference is 1.544MHz. Reserved. Skew Control Bits: These three bits control the delay of the DPLL outputs from 0 to 7 steps in interval of maximum unit delay of 3.5ns. 8-3 2-0 Unused SKC2 - SKC0 Table 23 - DPLL Output Adjustment (DPOA) Register Bits Read/Write Address: 002EH for DHKR Register Reset Value: 0000H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 SLS 5 PLS 4 CKM 3 Unused 2 Unused 1 Unused 3 Unused Bit 15 - 7 6 5 4 Name Unused SLS PLS CKM Description Reserved. Secondary Loss Detection Bit (Read-only bit): This bit is the same as the output from the DPLL Reference Monitor FAIL_SEC. Primary Loss Detection Bit (Read-only bit): This bit is the same as the output from the DPLL Reference Monitor FAIL_PRI. DPLL Clock Monitor Bit: When high, the primary output C32/64o is 65.536 MHz clock. When low, the primary output C32/64o is 32.768 MHz clock. This is the only writable bit in this register. Limit (Read-only bit): Indicates that DPLL Phase Slope limiter limits input phase. State: These 3 bits indicate the state of the DPLL State Machine. Please refer to Figure 16, "State Machine Diagram" on page 33. 3 2-0 Limit State State 2-0 000 001 010 011 100 101 110 111 State Name NORMAL_PRI Reserved HOLDOVER_PRI MTIE_PRI NORMAL_SEC Reserved HOLDOVER_SEC MTIE_SEC Table 24 - DPLL House Keeping (DHKR) Register Bits Zarlink Semiconductor Inc. 59 MT90866 15 BTM 2 14 BTM 1 13 BTM 0 12 BSAB 4 11 BSAB 3 10 BSAB 2 9 BSAB 1 8 BCA B0 7 BCA B7 6 BCA B6 5 BCA B5 4 BCA B4 3 BCA B3 2 BCA B2 Data Sheet 1 BCA B1 0 BCA B0 Bit 15 -13 Name BTM2 - 0 Description Throughput Delay and Message Control Bits: These three bits control the backplane CT-Bus input or output. BTM2-0 000 Throughput delay and Message Mode control Per-channel variable delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The backplane CT-Bus output is from local ST-BUS input. Per-channel constant delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The backplane CT-Bus output is from local ST-BUS input. Per-channel variable delay from backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The backplane CT-Bus output is from backplane CT-Bus input. Per-channel constant delay from backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The backplane CT-Bus output is from backplane CT-Bus input. Per-channel message mode; only the lower byte (bits 7 to 0) of the connection memory location will be the presented to the backplane CT-Bus output channel. Per-channel BER pattern; the pseudo random BER test pattern will be presented to the backplane CT-Bus output channel. Per-channel input. The backplane CT-Bus is input. Reserved. BTM1 BTM0 Input Source Local x x x x x x x x x Reserved Backplane Var. delay x x Const. delay Msg Mode BER I/O HiZ 001 010 011 100 101 110 111 BTM2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 12 - 8 7-0 (See Note 1) BSAB4 - BSAB0 BCAB7 - BCAB0 Source Stream Address Bits: These five bits refer to the number of the data streams for the source (local or backplane) connection. Source Channel Address Bits: These eight bits refer to the number of the channel that is the source (local or backplane) connection. Note 1: Only Bits 7-0 will be used for per-channel message mode for the backplane STio streams. Table 25 - Backplane Connection Memory Bits 60 Zarlink Semiconductor Inc. Data Sheet Data Rate 2 Mb/s 4 Mb/s 8 Mb/s 2-bit subrate 4-bit subrate Source Stream STi0-27 STi0-18 STi0-18 STi0-15 STi0-15 BSAB Bit Usage BSAB4-0 BSAB4-0 BSAB4-0 BSAB3-0 BSAB3-0 MT90866 BCAB Bit Usage BCAB4-0 (32-ch/frame) BCAB5-0 (64-ch/frame) BCAB6-0 (128-ch/frame) BCAB6-0 (128 ch/frame) BCAB5 -0 (64 ch/frame) Table 26 - BSAB and BCAB Bits Usage when Source Streams are from the Local Port Data Rate 8 Mb/s 16Mb/s Source Stream STio0-31 STio0-15 BSAB Bit Usage BSAB4-0 BSAB3-0 BCAB Bit Usage BCAB6-0 (128-ch/frame) BCAB7-0 (256 ch/frame) Table 27 - BSAB and BCAB Bits Usage when Source Streams are from the Backplane Port 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 LSRS1 0 LSRS0 Bit 15 - 2 1-0 Name Unused LSRS1 - LSRS0 Reserved. Sub-rate Switching Bits: Description For the 4-bit wide sub-rate switching: LSRS1 - 0 01 00 STo Output Bit 7 - 4 of the 8 bit data Bit 3 - 0 of the 8 bit data For 2-bit wide sub-rate switching: LSRS1 - 0 11 10 01 00 STo Output Bit 7 - 6 of the 8 bit data Bit 5 - 4 of the 8 bit data Bit 3 - 2 of the 8 bit data Bit 1 - 0 of the 8 bit data Table 28 - Local Connection Memory High Bits Zarlink Semiconductor Inc. 61 MT90866 15 LTM 2 14 LTM 1 13 LTM 0 12 LSAB 4 11 LSAB 3 10 LSAB 2 9 LSAB 1 8 LCAB 0 7 LCAB 7 6 LCAB 6 5 LCAB 5 4 LCAB 4 3 LCAB 3 2 LCAB 2 Data Sheet 1 LCAB 1 0 LCAB 0 Bit 15 -13 Name LTM2 - 0 Description Throughput Delay and Message Channel Control Bits: These three bits control the local ST-BUS output. LTM2-0 000 Throughput delay and Message Mode control Per-channel variable delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The local ST-BUS output is from the local ST-BUS input. Per-channel constant delay from local interface; the content of the connection memory is the local data memory address of the switched input channel and stream. The local ST-BUS output is from the local ST-BUS input. Per-channel variable delay from backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The local ST-BUS output is from the backplane CT-Bus input. Per-channel constant delay from the backplane interface; the content of the connection memory is the backplane data memory address of the switched input channel and stream. The local ST-BUS output is from backplane CT-Bus input. Per-channel message mode; only the lower byte (bits 7 to 0) of the connection memory location will be presented to the local ST-BUS output channel. Per-channel BER pattern; the pseudo random BER test pattern will be presented to the local ST-BUS output channel. Per-channel high-impedance. The local ST-BUS output is high-impedance. Reserved . 001 010 011 100 101 110 111 LTM2 LTM1 LTM0 Input Source Local x x x x Backplane Var. delay x Const. delay Msg Mode BER Output HiZ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x x x x x x Reserved 12 - 8 7-0 (See Note 1) LSAB4 LSAB0 LCAB7 LCAB0 Source Stream Address Bits: These five bits refer to the number of the data streams for the source (local or backplane) connection. Source Channel Address Bits: These eight bits refer to the number of the channel that is the source (local or backplane) connection. Table 29 - Local Connection Memory Low Bits 62 Zarlink Semiconductor Inc. Data Sheet Bit Name Description MT90866 Note 1: Only Bits 7-0 will be used for per-channel message mode for the local STo streams. Table 29 - Local Connection Memory Low Bits (continued) Data Rate 8 Mb/s 16Mb/s Source Stream STio0-31 STio0-15 LSAB Bit Usage LSAB4-0 LSAB3-0 LCAB Bit Usage LCAB6-0 (128-ch/frame) LCAB7-0 (256 ch/frame) Table 30 - LSAB and LCAB Bits Usage when Source Streams are from the Backplane Port Data Rate 2 Mb/s 4 Mb/s 8 Mb/s 2-bit subrate 4-bit subrate Source Stream STi0-27 STi0-18 STi0-18 STi0-15 STi0-15 LSAB Bit Usage LSAB4-0 LSAB4-0 LSAB4-0 LSAB3-0 LSAB3-0 LCAB Bit Usage LCAB4-0 (32-ch/frame) LCAB5-0 (64-ch/frame) LCAB6-0 (128-ch/frame) LCAB6-0 (128 ch/frame) LCAB5 -0 (64 ch/frame) Table 31 - LSAB and LCAB Bits Usage when Source Stream are from the Local Port Zarlink Semiconductor Inc. 63 MT90866 Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 Supply Voltage BSTio Bias Voltage Input Voltage Output Voltage Package power dissipation Storage temperature Symbol VDD VDD5V VI Vo PD TS - 55 Min -0.5 -0.5 -0.5 -0.5 Data Sheet Max 5.0 7.0 VDD + 0.5 VDD + 0.5 2 +125 Units V V V V W C * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 3 4 5 Operating Temperature Positive Supply BSTio Bias Voltage (3V PCI Spec) BSTio Bias Voltage (5V PCI Spec) Input Voltage Input Voltage on 5V Tolerant Inputs Sym TOP VDD VDD5V VDD5V VI VI_5V Min -40 3.0 3.0 4.5 0 0 Typ 25 3.3 3.3 5.0 Max +85 3.6 3.6 5.5 VDD VDD5V Units C V V V V V Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 4 Supply Current Input High Voltage Input Low Voltage Input Leakage (input pins) Sym IDD VIH VIL IL 0.7VDD 0.3VDD 15 Min Typ Max 480 Units mA V V A 0 < V < VDD_IO See Note 1 5 6 7 8 9 10 11 Weak Pullup Current Weak Pulldown Current Input Pin Capacitance Output High Voltage Output Low Voltage High Impedance Leakage Output Pin Capacitance IPU IPD CI VOH VOL IOZ CO 0.8VDD 0.4 5 15 33 33 5 50 50 10 A A pF V V A pF IOH = 10mA IOL = 10mA 0 < V < VDD_IO Input at 0V Input at VDD Test Conditions Output unloaded Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (Vin). 64 Zarlink Semiconductor Inc. Data Sheet MT90866 Characteristics Sym VCT VHM VLM Level 0.5VDD 0.7VDD 0.3VDD Units V V V Conditions AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels 1 2 3 CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low AC Electrical Characteristics - Input Frame Pulse and Input Clock Timing Characteristic 1 2 3 4 5 6 7 FRAME_A_io, FRAME_B_io Input Frame Pulse Width FRAME_A_io, FRAME_B_io Input Frame Pulse Setup Time FRAME_A_io, FRAME_B_io Input Frame Pulse Hold Time C8_A_io, C8_B_io Input Clock Period C8_A_io, C8_B_io Input Clock High Time C8_A_io, C8_B_io Input Clock Low Time Phase Correction Sym tCFPIW tCFPIS tCFPIH tC8MIP tC8MIH tC8MIL Min 90 45 45 122- 58- 58- 0 Typ 122 Max 180 90 90 122+ 64+ 64+ 10 5 Units Notes ns ns ns ns ns ns ns ns 8 C8_A_io, C8_B_io Input Rise/Fall Time trC8i, tfC8i 0 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. FRAME_A_io, FRAME_B_io (INPUT) tCFPIS CBFPIW tBFPH tC8MIP tC8MIL tC8MIH C8_A_io, C8_B_io (INPUT) Backplane Frame Boundary trC8i tfC8i Figure 24 - Backplane Frame Pulse Input and Clock Input Timing Diagram Zarlink Semiconductor Inc. 65 MT90866 Characteristic 1 2 3 Data Sheet AC Electrical Characteristics - Output Frame Pulse and Output Clock Timing Sym tFBOS Min 109.5 Typ 122 Max 8.0 134.5 -68.0 Units ns ns Notes Backplane Frame Boundary Offset FRAME_A_io, FRAME_B_io Output Pulse Width FRAME_A_io, FRAME_B_io Output Delay from Falling edge to Backplane Frame Boundary FRAME_A_io, FRAME_B_io Output Delayfrom Backplane Frame Boundary to Rising edge C8_A_io, C8_B_io Output Clock Period C8_A_io, C8_B_io Output High Time C8_A_io, C8_B_io Output Low Time C8_A_io, C8_B_io Output Rise Time C8_A_io, C8_B_io Output Fall Time C32/64o (32.768 MHz) Output Delay Time C32/64o (32.768 MHz) Period C32/64o (32.768 MHz) High Time C32/64o (32.768 MHz) Low Time C32/64o (65.536 MHz) Period C32/64o (65.536 MHz) High Time C32/64o (65.536 MHz) Low Time C32/64o Clock Rise Time (32.768 MHz or 65.536 MHz) C32/64o Clock Fall Time (32.768 MHz or 65.536 MHz) tCFPOW tCFODF CL=30pF ns 4 tCFODR 55 ns 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tC8MP tC8MH tC8ML trC8o tfC8o tC32MOD tC32MP tC32MH tC32ML tC32MP tC32MH tC32ML tr32o tf32o 115 54 54 122 129 68 68 13 14 7.0 ns ns ns ns ns ns ns ns ns ns ns ns ns CL=30pF CL=30pF 24 8.5 8.5 12 6 6 30.5 37 21.5 21.5 15.25 19.25 6.5 12.75 5 6 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 66 Zarlink Semiconductor Inc. Data Sheet MT90866 Backplane Frame Boundary tFBOS FRAME_A_io, FRAME_B_io (OUTPUT) tCFPOW tCFODR C8_A_io, C8_B_io (OUTPUT) tC8MH tC8ML tCFODF tC8MP tC32ML tC32MH C32/64o (32.768MHz) tC64ML C32/64o (65.536MHz) tC64MH trC8o tC32MP tC32MOD tfC8o tC64MP tC64MOD trC32o tfC32o Figure 25 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode and Secondary Master Mode) AC Electrical Characteristics - C20i Master Input Clock Timing Characteristic 1 2 3 4 5 Sym tC20MP tC20MH tC20ML trC20M, tfC20M Min 49.995 -100 20 20 Typ 50 Max 50.005 100 30 30 10 Units ns ppm ns ns ns Notes C20i Input Clock Period C20i Input Clock Tolerance C20i Input Clock High Time C20i Input Clock Low Time C20i Input Rise/Fall Time Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. tC20MP tC20ML C20i trC20M tfC20M tC20MH Figure 26 - Backplane Frame Pulse Input and Clock Input Timing Diagram Zarlink Semiconductor Inc. 67 MT90866 AC Electrical Characteristics - Reference Input Timing Characteristic 1 2 3 4 5 6 7 8 9 CTREF1, CTREF2, LREF0-7 Period CTREF1, CTREF2, LREF0-7 High Time CTREF1, CTREF2, LREF0-7 Low Time CTREF1, CTREF2, LREF0-7 Rise/Fall Time CTREF1, CTREF2, LREF0-7 Period CTREF1, CTREF2, LREF0-7 High Time CTREF1, CTREF2, LREF0-7 Low Time CTREF1, CTREF2, LREF0-7 Rise/Fall Time CTREF1, CTREF2, LREF0-7 Period Sym tR8KP tR8kh tR8kL trR8K, tfR8K tR2MP tR2Mh tR2ML trR2M, tfR2M tR1M5P tR1M5h tR1M5L trR1M5, tfR1M5 Min 121 0.09 0.09 0 366 90 90 0 486 90 90 0 648 324 324 488 244 244 Typ 125 Max 129 128.91 128.91 20 610 520 520 20 810 720 720 20 Units s s s ns ns ns ns ns ns Data Sheet Notes 8kHz Mode 2.048MHz Mode 10 CTREF1, CTREF2, LREF0-7 High Time 11 CTREF1, CTREF2, LREF0-7 Low Time 12 CTREF1, CTREF2, LREF0-7 Rise/Fall Time ns ns ns 1.544MHz Mode Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. tR8KP CTREF1, CTREF2, LREF0-7 (8kHz) tR8KH tR8KL trR8K tfR8K Figure 27 - Reference Input Timing Diagram when the input frequency = 8kHz tR2MP CTREF1, CTREF2, LREF0-7 (2.048MHz) tR2ML tR2MH trR2M tfR2M Figure 28 - Reference Input Timing Diagram when the input frequency = 2.048MHz tR1M5P CTREF1, CTREF2, LREF0-7 (1.544MHz) tR1M5L tR1M5H trR1M5 tfR1M5 Figure 29 - Reference Input Timing Diagram when the input frequency = 1.544Hz 68 Zarlink Semiconductor Inc. Data Sheet AC Electrical Characteristics - Reference Output Timing Characteristic 1 NREFo Output Delay Time 2 NREFo Clock Period 3 NREFo Clock High Time 4 NREFo Clock Low Time 5 NREFo Clock Rise/Fall Time 6 NREFo Clock Period 7 NREFo Clock High Time 8 NREFo Clock Low Time 9 NREFo Clock High Time 10 NREFo Clock Low Time Sym tROD tRP tRH tRL trREF, tfREF tR8KOP tR8KO2H tR8KO2L tR8KO15H tR8KO15L Same as LREF0-7 Period Same as LREF0-7 High Time Same as LREF0-7 Low Time 0 124.9 124.4 481 124.3 641 125 124.5 488 124.4 648 12 14 125.1 124.6 495 124.5 655 ns s s ns s ns Min Typ Max 20 Units ns MT90866 Notes (DIV1,DIV0) = (0,0) in the DOM2 Register (DIV1,DIV0) = (0,1) or (DIV1,DIV0) = (1,0) in the DOM2 Register Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. LREF0-7 (8KHz) NREFo (8KHz) tROD tRP tRH tfREF tRL trREF Figure 30 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register LREF0-7 (2.048MHz) NREFo (2.048MHz) tROD tRP tRL tRH trREF tfREF Figure 31 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register LREF0-7 (1.544MHz) NREFo (1.544MHz) tROD tRP tRL trREF tRH tfREF Figure 32 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register LREF0-7 (2.048MHz) NREFo (8KHz) tROD tR8KO2L trREF tfREF tR8KOP tR8KO2H Figure 33 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register Zarlink Semiconductor Inc. 69 MT90866 LREF0-7 (1.544MHz) NREFo (8KHz) tROD tR8KO15L trREF tfREF tR8KOP Data Sheet tR8KO15H Figure 34 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register AC Electrical Characteristics - Local Frame Pulse and Clock Timing, ST_CKo = 4.096MHz Characteristic 1 2 3 Local Frame Boundary Offset1 ST_FPo0/1 Width ST_FPo0/1 Output Setup from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 ST_FPo 0/1Output Hold from Falling edge of ST_CKo0/1 to rising edge of ST_FPo0/1 5 6 7 8 ST_CKo0/1 Clock Period ST_CKo0/1 Clock Pulse Width High ST_CKo0/1 Clock Pulse Width Low ST_CKo0/1 Clock Rise/Fall Time tCP4 tCh4 tCL4 trC4o, tC4o 237 115 115 244 251 129 129 14 ns ns ns ns Sym tLFBOS tFPW4 tFODF4 237 115 Min Typ Max 28 251 129 Units ns ns ns CL=30pF tFODR4 115 129 ns Notes 4 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: No jitter presented on input reference clock. Backplane Frame Boundary Local Output Frame Boundary tLFBOS tFPW4 ST_FPo0/1 tFODF4 tCP4 tCH4 ST_CKo0/1 (4.096MHz) tfC4o trC4o tCL4 tFODR4 Figure 35 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096MHz 70 Zarlink Semiconductor Inc. Data Sheet MT90866 Characteristic Sym tLFBOS tFPW8 tFODF8 tFODR8 tCP8 tCh8 tCL8 trC8o, tfC8o 115 54 54 115 54 54 122 Min Typ Max 28 129 68 68 129 68 68 14 Units ns ns ns ns ns ns ns ns CL=30pF Notes AC Electrical Characteristics - Local Frame Pulse and Clock Timing, ST_CKo0 = 8.192MHz 1 2 3 4 5 6 7 8 Local Frame Boundary Offset1 ST_FPo0/1 Width ST_FPo0/1 Output Setup from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 ST_FPo0/1 Output Holdfrom Falling edge of ST_CKo0-1 to rising edge of ST_FPo0/1 ST_CKo0/1 Clock Period ST_CKo0/1 Clock Pulse Width High ST_CKo0/1 Clock Pulse Width Low ST_CKo0/1 Clock Rise/Fall Time Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: No jitter presented on input reference clock. Backplane Frame Boundary Local Output Frame Boundary tLFBOS tFPW8 ST_FPo0/1 tFODF8 tCL8 ST_CKo0/1 (8.192MHz) tCH8 tFODR8 tCP8 trC8o tfC8o Figure 36 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192MHz Zarlink Semiconductor Inc. 71 MT90866 Characteristic 1 2 3 Local Frame Boundary Offset1 ST_FPo0/1 Width ST_FPo0/1 Output Setup from Falling edge of ST_FPo0/1 to falling edge of ST_CKo0/1 ST_FPo Output Hold from Falling edge of ST_CKo0/1 to rising edge of ST_FPo0/1 5 6 7 8 ST_CKo0/1 Clock Period ST_CKo0/1 Clock Pulse Width High ST_CKo0/1 Clock Pulse Width Low ST_CKo0/1 Clock Rise/Fall Time tCP16 tCh16 tCL16 trC16o, tfC16o 54 23 23 61 68 37 37 15 ns ns ns ns Sym tLFBOS tFPw16 tFODF16 54 23 Min Typ Max 28 68 37 Units ns ns ns Data Sheet AC Electrical Characteristics - Local Frame Pulse and Clock Timing, ST_CKo = 16.384MHz Notes 4 tFODR16 23 37 ns CL=30pF Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Note 1: No jitter presented on input reference clock. Backplane Frame Boundary tLFBOS tFPW16 Local Output Frame Boundary ST_FPo0/1 tFODF16 tCL16 tCH16 tFODR16 tCP16 ST_CKo0/1 (8.192MHz) trC16o tfC16o Figure 37 - Local Clock Timing Diagram when ST_CKo frequency = 16.384MHz AC Electrical Characteristics- C1M5o Output Clock Timing Characteristic 1 2 3 4 5 C1M5o Period C1M5o High Time C1M5o Low Time C1M5o Rise Time C1M5o Fall Time Sym tC1M5oP tC1M5oH tC1M5oL trC1M5o tfC1M5o Min Typ 648 324 324 10 11 Max Units ns ns ns ns ns Notes CL=30pF Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 72 Zarlink Semiconductor Inc. Data Sheet MT90866 C1M5o (1.544MHz) trC1M5o tC1M5oL tC1M5oP tC1M5oH tfC1M5o Figure 38 - C1M5o Output Clock Timing Diagram AC Electrical Characteristics - Backplane Serial Streams with Date Rate of 8Mb/s Characteristic 1 2 3 4 5 STio0-31 Input Data Sample Point STio0-31 Input Setup Time STio0-31 Input Hold Time STio0-31 Output Delay Active to Active Per Channel boundary HiZ Sym tSAMP8 tCIS8 tCIH8 tDOD8 tDOZ8 tZDO8 Min 84 11.5 11.5 Typ Max 98 Units ns ns ns ns ns ns Test Conditions 11 10 10 CL = 30pF, Note 1 RL=1K, CL=30pF, Note 2 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: To meet the H.110 output timing requirement, the output delay time can be reduced further by programming the backplane output advancement registers (BOA0 - 3). * Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L. FRAME_A_io, FRAME_B_io C8_A_io, C8_B_io (8.192MHz) tSAMP8 tCIS8 tCIH8 Bit 0 Ch 0 Bit 1 Ch 0 Bit 2 Ch 0 Bit 3 Ch 0 Bit 4 Ch 0 STio (8Mb/s) Backplane input Bit 6 Ch127 Bit 7 Ch127 VTT tZDO8 tDOD8 Bit 0 Ch 0 Bit 1 Ch 0 Bit 2 Ch 0 Bit 3 Ch 0 Bit 4 Ch 0 STio (8Mb/s) Backplane output Bit 6 Ch127 Bit 7 Ch127 VTT tDOZ8 Figure 39 - Backplane Serial Stream Timing when the Data Rate is 8Mb/s Zarlink Semiconductor Inc. 73 MT90866 Characteristic 1 2 3 4 STio0-15 Input Data Sample Point STio0-15 Input Setup Time STio0-15 Input Hold Time STio0-15 Output Delay Active to Active Sym tSAMP16 tCIS16 tCIH16 tDOD16 Min 38 12 12 11 Typ Max 52 Units ns ns ns ns Data Sheet AC Electrical Characteristics - Backplane Serial Streams with Date Rate of 16Mb/s Test Conditions CL = 30pF Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. FRAME_A_io, FRAME_B_io C8_A_io, C8_B_io (8.192MHz) tCIS16 tSAMP16 tCIH16 Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 Ch 0 Bit 4 Ch 0 Bit 3 Ch 0 Bit 2 Ch 0 Bit 1 Ch 0 Bit 0 Ch 0 Bit 7 Ch 1 Bit 6 Ch 1 STio (16Mb/s) Backplane input Bit 3 Ch255 Bit 1 Bit 2 Ch255 Ch255 Bit 0 Ch255 VTT tDOD16 STio (16Mb/s) Backplane output Bit 3 Ch255 Bit 1 Bit 2 Ch255 Ch255 Bit 0 Ch255 Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 Ch 0 Bit 4 Ch 0 Bit 3 Ch 0 Bit 2 Ch 0 Bit 1 Ch 0 Bit 0 Ch 0 Bit 7 Ch 1 Bit 6 Ch 1 VTT Figure 40 - Backplane Serial Stream Timing when the Data Rate is 16Mb/s 74 Zarlink Semiconductor Inc. Data Sheet AC Electrical Characteristics - Local Serial Stream Timing Characteristic 1 STi Setup Time 2.048Mb/s 4.096Mb/s 8.192Mb/s STi Hold Time 2.048Mb/s 4.096Mb/s 8.192Mb/s STo Delay - Active to Active @2.048Mb/s @4.096Mb/s @8.192Mb/s Sym tSIS2 tSIS4 tSIS8 tSIH2 tSIH4 tSIH8 tSOD2 tSOD4 tSOD8 Min 12 12 12 12 12 12 5 5 5 Typ Max Units ns ns ns ns ns ns ns ns ns MT90866 Test Conditions 2 3 CL = 30pF CL = 30pF CL = 30pF Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. ST_FPo0/1, ST_CKo0/1 tSAMP8 tSIS8 tSIH8 Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 Ch 0 Bit 4 Ch 0 Bit 3 Ch 0 STi (8Mb/s) Local input Bit 1 Ch 0 Bit 0 Ch 0 VTT tSOD8 STo (8Mb/s) Local output Bit 1 Ch127 Bit 0 Ch127 Bit 7 Ch 0 Bit 6 Ch 0 Bit 5 Ch 0 Bit 4 Ch 0 Bit 3 Ch 0 VTT tSIS4 tSIH4 Bit 7 Ch 0 Bit 6 Ch 0 STi (4Mb/s) Local input STo (4Mb/s) Local output Bit 0 Ch63 VTT tSOD4 Bit 7, Ch 0 VTT tSIS2 tSIH2 Bit 7 Ch 0 STi (2Mb/s) Local input STo (2Mb/s) Local output Bit 0 Ch31 VTT tSOD2 Bit 0, Ch 31 Bit 7, Ch 0 VTT Figure 41 - Local Serial Stream Timing Zarlink Semiconductor Inc. 75 MT90866 ST_FPo0/1 ST_CKo0/1 (8.192MHz) tSOD2 STo0-15 (2Mb/s) 4-bit wide output STi0-15 (2Mb/s) 4-bit wide input Bit 0, Ch 63 Bit 3, Ch 0 Bit 2, Ch 0 Bit 1, Ch 0 Bit 0, Ch 0 Data Sheet VTT tSIS2 Bit 0, Ch 63 Bit 3, Ch 0 tSIH2 Bit 2, Ch 0 Bit 1, Ch 0 Bit 0, Ch 0 VTT tSOD2 STo0-15 (2Mb/s) 2-bit wide output STi0-15 (2Mb/s) 2-bit wide input Bit 0, Ch 127 Bit 1, Ch 0 Bit 0, Ch 0 Bit 1, Ch 1 Bit 0, Ch 1 VTT tSIS2 Bit0,Ch127 Bit1, Ch0 tSIH2 Bit 0, Ch 0 Bit 1, Ch 1 Bit 0, Ch1 VTT Figure 42 - Sub-rate Switching Timing for Local Streams (2 & 4-bit wide) 76 Zarlink Semiconductor Inc. Data Sheet AC Electrical Characteristics - Local and Backplane Tristate Timing Characteristic 1 STo/STio Delay - Active to High-Z - High-Z to Active 2.048 Mb/s (local) 4.096 Mb/s (local) 8.192 Mb/s (local) 8.192 Mb/s (backplane) 16.384 Mb/s (backplane) 2 Output Driver Enable (ODE) Delay - High-Z to Active 2.048 Mb/s (local) 4.096 Mb/s (local) 8.192 Mb/s (local) 8.192 Mb/s (backplane) 16.384 Mb/s (backplane) Output Driver Disable (ODE) Delay - Active to High-Z 2.048 Mb/s (local) 4.096 Mb/s (local) 8.192 Mb/s (local) 8.192 Mb/s (backplane) 16.384 Mb/s (backplane) Sym tDZ, tZD Min Typ Max Units MT90866 Test Conditions 33 33 33 22 22 ns ns ns ns ns RL=1K, CL=30pF, See Note 1. tZD_ODE 37 37 37 20 20 ns ns ns ns ns 2 tDZ_ODE 20 20 20 20 20 ns ns ns ns ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L. CLK tDZ STo Valid Data tZD STo Tri-state VTT Tri-state VTT Valid Data VTT Figure 43 - Serial Output and External Control ODE tZD_ODE STo HiZ Valid Data tDZ_ODE HiZ VTT VTT Figure 44 - Output Driver Enable (ODE) Zarlink Semiconductor Inc. 77 MT90866 AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 2 3 4 5 6 7 8 9 11 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA Low on Read Data hold on read Valid Write Data Setup Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Sym tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tWDS tDHW tAKD 8 97/82 110/95 158/114 171/127 30 Min 0 15 5 0 0 5 20 20 20 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet Test Conditions1 CL=30pF CL=30pF, RL=1K See Note 2 10 Data hold on write CL=30pF CL=30pF CL=30pF, RL=1K, See Note 2 12 Acknowledgment Hold Time tAKH Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. *Note 1: A delay of 100 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high. *Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L . DS tCSS CS tRWS R/W tADS A0-A13 VALID ADDRESS VTT tCSH VTT tRWH VTT tADH VTT tDHR D0-D15 READ tWDS D0-D15 WRITE VALID READ DATA VTT tDHW VALID WRITE DATA VTT tDDR DTA tAKD tAKH VTT Figure 45 - Motorola Non-Multiplexed Bus Timing 78 Zarlink Semiconductor Inc. Data Sheet AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW tRSTW 20 400 Min 200 80 80 10 10 20 20 30 Typ Max MT90866 Units ns ns ns ns ns ns ns ns ns ns CL=30pF CL=30pF CL=30pF Notes 10 Reset pulse width Characteristics are over recommended operating conditions unless otherwise stated. tTCKL TCK tTCKH tTCKP tTMSS TMS tTMSH tTDIS tTDIH TDi tTDOD TDo tTRSTW TRST Figure 46 - JTAG Test Port Timing Diagram tRSTW Reset Figure 47 - Reset Pin Timing Diagram Zarlink Semiconductor Inc. 79 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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